Skip to main content

The performance of software-managed multiprocessor caches on parallel numerical programs

  • Session 4A: Compilers And Restructuring Techniques I
  • Conference paper
  • First Online:

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 297))

This is a preview of subscription content, log in via an institution.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. W. Abu-Sufah and A. Y. Kwok, “Performance Prediction Tools for Cedar: A Multiprocessor Supercomputer,” The 12th Annual International Symposium on Computer Architecture, pp. 406–413, June, 1985.

    Google Scholar 

  2. W. Crowther et al, “Performance Measurements on 128-node Butterfly(−) Parallel Processor,” Proceedings of the 1985 International Conference on Parallel Processing, pp. 531–540, 1985.

    Google Scholar 

  3. S.H. Fuller and S.P. Harbison, “The C.mmp Multiprocessor,” Department of Computer Science, Carnegie-Mellon University, Technical Report, 1978.

    Google Scholar 

  4. A. Gottlieb, R. Grishman, C.P. Kruskal, K.P. McAuliffe, L. Rudolph, and M. Snir, "The NYU Ultracomputer — Designing an MIMD Shared-Memory Parallel Machine," IEEE Trans. on Computers, Vol. C-32, No. 2, pp. 175–189, February 1983.

    Google Scholar 

  5. Daniel Gajski, David Kuck, Duncan Lawrie, and Ahmed Sameh, “Cedar — a Large Scale Multiprocessor,” Proceedings of the 1983 International Conference on Parallel Processing, pp. 524–529, August, 1983.

    Google Scholar 

  6. J.R. Goodman, “Using Cache Memory to Reduce Processor-Memory Traffic,” Proceedings 10th International Symposium on Computer Architecture, pp. 124–131, June, 1983.

    Google Scholar 

  7. W. Jalby, and U. Meier, “Optimizing Matrix Operations on a Parallel Multiprocessor with a Hierarchical Memory System” Proceedings 1986 ICPP, pp.429–432, August, 1986.

    Google Scholar 

  8. David J. Kuck, “The Structure of Computers and Computations,” Volume 1, John Wiley and Sons, New York, 1978.

    Google Scholar 

  9. D.J. Kuck, R.H. Kuhn, B. Leasure, and M. Wolfe, “The Structure of an Advanced Vectorizer for Pipelined Processors,” Fourth International Computer Software and Applications Conference, October, 1980.

    Google Scholar 

  10. D. H. Lawrie, “Access and Alignment of Data in an Array Processor,” IEEE Transactions on Computers, vol. C-24, no. 12, pp. 1145–1155, December, 1975.

    Google Scholar 

  11. S. F. Lundstrom and G. H. Barnes, “Controllable MIMD Architecture,” Proceedings of the 1980 International Conference on Parallel Processing, pp. 19–27, 1980.

    Google Scholar 

  12. D.A. Padua Haiek, "Multiprocessors: Discusions of Some Theoretical and Practical Problems," Ph.D. Thesis, University of Illinois at Urbana-Champaign, DCS Report No. UIUCDCS-R-79-990, November 1979.

    Google Scholar 

  13. G.F. Pfister et al, “The IBM Research Parallel Processor Prototype,” Proceedings of the 1985 International Conference on Parallel Processing, pp. 764–772, 1985.

    Google Scholar 

  14. A. J. Smith, “Cache Memories,” Computing Surveys, Vol. 14, No.3, pp. 473–530, September 1982.

    Google Scholar 

  15. C. K. Tang, “Cache System Design in the Tightly Coupled Multiprocessor System,” Proceedings AFIP National Computer Conference, vol.45, pp. 749–753, 1976.

    Google Scholar 

  16. Michael J. Wolfe, “Optimizing Supercompilers for Supercomputers,” Ph.D. Thesis, University of Illinois at Urbana-Champaign, 1982.

    Google Scholar 

  17. A. V. Veidenbaum, “A Compiler-Assisted Cache Coherence Solution for Multiprocessors,” Proceedings of the 1986 International Conference on Parallel Processing, pp. 1029–1036, 1986.

    Google Scholar 

  18. W.C. Yen, J.H. Patel, E.S. Davidson. “Shared Cache for Multiple-Stream Computer Systems,” IEEE Trans. on Computers, Vol. C-34, No. 1, pp. 56–65, January, 1983.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

E. N. Houstis T. S. Papatheodorou C. D. Polychronopoulos

Rights and permissions

Reprints and permissions

Copyright information

© 1988 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Cheong, H., Veidenbaum, A.V. (1988). The performance of software-managed multiprocessor caches on parallel numerical programs. In: Houstis, E.N., Papatheodorou, T.S., Polychronopoulos, C.D. (eds) Supercomputing. ICS 1987. Lecture Notes in Computer Science, vol 297. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-18991-2_19

Download citation

  • DOI: https://doi.org/10.1007/3-540-18991-2_19

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-18991-6

  • Online ISBN: 978-3-540-38888-3

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics