Abstract
GRIP is a high-performance parallel machine designed to execute functional programs using supercombinator graph reduction. It uses a high-bandwidth bus to provide access to a large, distributed shared memory, using intelligent memory units and packet-switching protocols to increase the number of processors which the bus can support. GRIP is also being programmed to support parallel Prolog and DACTL.
We outline GRIP's architecture and firmware, discuss the major design issues, and describe the current state of the project and our plans for the future.
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Clack CD and Peyton Jones SL, "The four-stroke reduction engine", ACM Conference on Lisp and Functional Programming, Boston, Aug 1986.
Darlington J and Reeve M, "ALICE — a multiprocessor reduction machine for the parallel evaluation of applicative languages", Proc ACM conference on Functional Programming Languages and Computer Architecture, New Hampshire, pp65–75, Oct 1981.
Dijkstra EW, Feijen WHJ and van Gasteren AJM, "Derivation of a termination detection algorithm of distributed computations", in Control Flow and Data Flow — Concepts of Distributed Programming, ed Broy, Springer-Verlag, 1985.
Johnsson, T, "Compiling lazy functional languages", PhD thesis, Programming Methodology Group, Chalmers University, Goteborg, 1987.
Peyton Jones, SL, "The implementation of functional programming languages", Prentice Hall, 1987.
Sargeant, J. "Load balancing, locality and parallelism control in fine-grain parallel machines", Department of Computer Science, University of Manchester, Nov 1986.
Stoye WR, Clarke TJW and Norman AC, "Some practical methods for rapid combinator reduction", Proc ACM Symposium on Lisp and Functional Programming, Austin, pp159–166, Aug 1984.
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© 1987 Springer-Verlag Berlin Heidelberg
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Jones, S.L.P., Clack, C., Salkild, J., Hardie, M. (1987). GRIP — a high-performance architecture for parallel graph reduction. In: Kahn, G. (eds) Functional Programming Languages and Computer Architecture. FPCA 1987. Lecture Notes in Computer Science, vol 274. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-18317-5_7
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DOI: https://doi.org/10.1007/3-540-18317-5_7
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