Technological developments for three-dimensional circuitry

Abstract

For architectures which allow parallel processing it is necessary to increase the dimensionality of the device arrangement as well as the complexity of the connecting network. For this purpose the classical two-dimensional arrangement of active elements and connections which is predetermined by planar semiconductor technology must be extended in the third dimension. Presently the research activities are concentrated in three different areas: (a) more efficient connection networks between chips, (b) extension of planar technology by one or two additional single crystalline layers for active elements on top of the amorphous insulator (SOI), and (c) growth of multilevel systems by epitaxial techniques. All of these methods have to overcome considerable problems before they are applicable for mass production. The highest degree of complexity can be expected from epitaxial methods if masking procedures can be developed which allow in-situ doping in the growth chamber.