Abstract
The purpose of this paper is two-fold. Firstly, it introduces and develops the ideas of the Linear Instruction Systolic Array (LISA), and shows that it can simulate MIMD, SIMD and Systolic Wavefront Processor Algorithms involving nobacktracking.
Secondly, we show that it can be used to develop a powerful Parallel Architecture based on LISA chips, which should be expandable and area efficient.
As a subsidiary argument we can also demonstrate that there is real evidence for the role of Systolic Computation particularly pipelining in the development of parallel computations.
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References
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© 1986 Springer-Verlag Berlin Heidelberg
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Megson, G.M., Evans, D.J. (1986). Lisa: A parallel processing architecture. In: Händler, W., Haupt, D., Jeltsch, R., Juling, W., Lange, O. (eds) CONPAR 86. CONPAR 1986. Lecture Notes in Computer Science, vol 237. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-16811-7_191
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DOI: https://doi.org/10.1007/3-540-16811-7_191
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