Abstract
A new design method of TSC m-out-of-2m code checkers is presented. The design is composed basically of two full-adder/half-adder trees, each summing-up the one's of m input lines, and a k-variable 2-pair two-rail code tree that compares the outputs of the two adder trees. The only modules used are full-adders, half-adders and two-rail T2. This method is well suited for VLSI MOS implementation and compared to previous methods it results in significant circuit cost reduction and smaller test set, without sacrificing performance. At the same time the proposed design has all added advantages of a modular design.
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
V. References
W.C. Carter and P.R. Schneider," Design of dynamically checked computers", IFIP Congr. 68, Vol.2, pp. 878–883, Edinburg, Scotland, 1968.
D.A. Anderson and G. Metze," Design of totally self-checking check circuits for m-out-of-n codes", IEEE Trans. on Comp., vol.22, pp. 263–269, March 1973.
J.F. Wakerly," Error Detecting codes, Self-Checking Circuits and Applications", New York: Elsevier-North Holland, New York, 1978.
S.M. Reddy," A note on self-checking checkers", IEEE Trans. on Comp., vol. 23, pp 1100–1102, Oct. 1974.
S.M. Reddy and J.R. Wilson," Easily testable cellular realizations for the (exactly P)-out-of-n and (P or more)-out-of-n logic functions", IEEE Trans. on Comp., vol. 23, pp. 98–100, Jan. 1974.
J.E.Smith," Design of totally self-checking check circuits for a class of unordered codes", Design Automation and Fault-Tolerant Computing, pp.321–343, Oct. 1977.
N. Gaitanis and C. Halatsis," A new design method for m-out-of-n TSC checkers", IEEE Trans. on Computers, vol. 32, pp.273–283, Mar. 1983.
C. Efstathiou, C. Halatsis," Efficient modular design of m-out-of-2m TSC checkers, for m=2k−1, k≥2", Electr. Letters, vol. 21, N. 23, pp. 1083–1084, 7th Nov. 1985.
Y. Crouzet and C. Landrault," Design of self-checking MOS-LSI circuits: application to a four-bit microprocessor", IEEE Trans. on Comp., vol. 29, pp.532–537, June 1980.
N.Jha and J.Abraham," Techniques for efficient MOS implementation of totally self-checking checkers", Proc. of 15th FTCS, June 1985.
J. Galiay, Y. Crouzet and M. Vergniault," Physical versus logical fault models in MOS LSI circuits: Impact on their testability", IEEE Trans. on Comp., vol.29, pp. 527–531, June 1980.
N. Jha and J. Abraham," Totally self-checking MOS circuits under realistic physical failures", International Conference on Computer Design, Port Chester, New York, Oct. 1984.
D.A. Anderson," Design of self-checking digital networks using coding techniques", Coordinated Science Lab., Rep. R-527, Un. of Illinois, Urbana, Oct. 1971.
M.Nicolaidis, I.Jansch and B.Courtois," Strongly code-disjoint checker", Proc. of 14th FTCS, June 1984.
M.Marouf and A.Friedman," Design of self-checking checkers for Berger codes", Proc. of 8th FTCS pp. 179–184, June 1978.
Y. Tamir and C. Seguin," Design and application of self-testing comparators implemented with MOS PLA's", IEEE Trans. on Comp., vol. 33, pp. 493–506, June 1984.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1986 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Paschalis, A.M., Nikolos, D., Halatsis, C. (1986). Efficient modular design of TSC checkers for m-out-of-2m codes. In: Makedon, F., Mehlhorn, K., Papatheodorou, T., Spirakis, P. (eds) VLSI Algorithms and Architectures. AWOC 1986. Lecture Notes in Computer Science, vol 227. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-16766-8_13
Download citation
DOI: https://doi.org/10.1007/3-540-16766-8_13
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-16766-2
Online ISBN: 978-3-540-38746-6
eBook Packages: Springer Book Archive