A portable logic simulation system for development of FLATS machine

Abstract

This paper describes a portable logic simulation system PLS, which was used for development of FLATS — a formula manipulation machine consisting of more than 33,000 ECL and partly TTL MSI chips. The themes of this paper are practice and experience in developing such a large machine as FLATS in the research laboratories of the university and the institute. PLS supports two simulation languages, HDL (Hardware Description Language) and SCL (Simulation Control Language). Register-transfer and/or gate level design specifications are written in HDL. SCL describes control information about the simulation. Both descriptions are translated into Fortran and are linked to execute the simulation. The PLS system is implemented mainly in Fortran. Fortran was used for portability and efficiency. PLS checks for several types of illegal specifications globally at compile time and executes one-pass simulation; thereby the execution time is considerably shortened. The system covers a wide area of application and its conciseness facilitates expressing, organizing, and in general, dealing with large digital systems. In the development of FLATS, PLS is also used as a maintenance tool which generates test data to make it possible to compare the simulation results with the status of the actual hardware system. This paper also describes a preprocessor RATFOR-LS, which is an extension of RATFOR in bit-manipulating operations to facilitate describing and simulating computer hardware.