Abstract
The catastrophic fault pattern is a pattern of faults occurring at strategic locations that may render a system unusable regardless of its component redundancy and of its reconfiguration capabilities. In this paper, we characterize catastrophic fault patterns in mesh networks when the links are bidirectional or unidirectional. We determine the minimum number of faults required for a fault pattern to be catastrophic. We consider the problem of testing whether a set of faulty processors is catastrophic. In addition, when a fault pattern is not catastrophic we consider the problem of finding optimal reconfiguration strategies, where optimality is with respect to either the number of processing elements in the reconfigured network (the reconfiguration is optimal if such a number is maximized) or the number of bypass links to activate in order to reconfigure the array (the reconfiguration is optimal if such a number is minimized). The problem of finding a reconfiguration strategy that is optimal with respect to the size of the reconfigured network is NP-complete, when the links are bidirectional, while it can be solved in polynomial time, when the links are unidirectional. Considering optimality with respect to the number of bypass links to activate, we provide algorithms which efficiently find an optimal reconfiguration.
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References
Balasubramanian, V., Banerjee, P.: A fault tolerant massively parallel processing architechture. Journal of Parallel and Distributed Computing 4, 363–383 (1987)
Bruck, J., Cypher, R., Ho, C.T.: Fault-tolerant meshes with minimal number of spares. In: Proc. of 3rd IEEE Symposium on Parallel and Distributed Processing, pp. 288–295 (1991)
De Prisco, R., Monti, A., Pagli, L.: Efficient testing and reconfiguration of VLSI linear arrays. Theoretical Computer Science 197, 105–129 (1998)
De Prisco, R., De Santis, A.: Catastrophic faults in reconfigurable systolic linear arrays. Discrete Applied Math. 75, 105–123 (1997)
Cormen, T.H., Lierson, C.E., Rivest, R.L., Stein, C.: Introduction to Algorithms. MIT Press, Cambridge
Garey, M., Johnson, D.: Computers and intractability. Freeman, New York (1979)
Kung, H.T.: Why systolic architecture? IEEE Computer 15, 37–46 (1982)
Maity, S., Roy, B., Nayak, A.: Enumerating catastrophic fault patterns in VLSI arrays with both uni- and bidirectional links. INTEGRATION: The VLSI Journal 30, 157–168 (2001)
Maity, S., Nayak, A., Roy, B.: On Characterization of Catastrophic Faults in Two-Dimensional VLSI Arrays. INTEGRATION, The VLSI Journal 38, 267–281 (2004)
Maity, S., Roy, B., Nayak, A.: On Enumeration of Catastrophic Fault Patterns. Information Processing Letters 81, 209–212 (2002)
Maity, S., Nayak, A., Roy, B.: Reliability of VLSI Linear Arrays with Redundant Links. In: Sen, A., Das, N., Das, S.K., Sinha, B.P. (eds.) IWDC 2004. LNCS, vol. 3326, pp. 326–337. Springer, Heidelberg (2004)
Nayak, A., Pagli, L., Santoro, N.: Efficient construction of catastrophic patterns for VLSI reconfigurable arrays. INTEGRATION: The VLSI Journal 15, 133–150 (1993)
Nayak, A., Pagli, L., Santoro, N.: On testing of catastrophic faults in reconfigurable arrays with arbitrary link redundancy. INTEGRATION: The VLSI Journal 20, 327–342 (1996)
Nayak, A., Santoro, N., Tan, R.: Fault-Intolerance of reconfigurable systolic arrays. In: Proc. of 20th Int. Symp. on Fault-Tolerant Computing, pp. 202–209 (1990)
Leighton, T., Leiserson, C.E.: Wafer-scale integration of systolic arrays. IEEE Trans. on Computers C-34, 448–461 (1985)
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Maity, S., Nayak, A., Ramsundar, S. (2006). On Fault Tolerance of Two-Dimensional Mesh Networks. In: Chaudhuri, S., Das, S.R., Paul, H.S., Tirthapura, S. (eds) Distributed Computing and Networking. ICDCN 2006. Lecture Notes in Computer Science, vol 4308. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11947950_49
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DOI: https://doi.org/10.1007/11947950_49
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-68139-7
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