Abstract
In the case of simple tile-based architecture, such as small reconfigurable processor arrays, a virtual-channel mechanism, which requires additional logic and pipeline stages, will be one of the crucial factors for a low cost implementation of their on-chip routers. To guarantee deadlock-free packet transfer with no virtual channels on tori, we propose a non-minimal strategy consistent with the rule of dimension-order routing (DOR) algorithm. Since embedded streaming applications usually generate predictable data traffic, the path set can be customized to the traffic from alternative DOR paths. Although the proposed strategy does not use any virtual channels, it achieves almost the same performance as virtual-channel routers on tori in eleven of 18 application traces.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Benini, L., Micheli, G.D.: Networks on Chips: A New SoC Paradigm. IEEE Computer 35(1), 70–78 (2002)
Dally, W.J., Towles, B.: Route Packets, Not Wires: On-Chip Interconnection Networks. In: Proceedings of the Design Automation Conference, pp. 684–689 (2001)
Burger, D., et al.: Scaling to the End of Silicon with EDGE Architectures. IEEE Computer 37(7), 44–55 (2004)
Liang, J., et al.: An Architecture and Compiler for Scalable On-Chip Communication. IEEE Transactions on Very Large Scale Integration Systems 12(7), 711–726 (2004)
Taylor, M.B., et al.: The Raw Microprocessor: A Computational Fabric for Software Circuits and General Purpose Programs. IEEE Micro 22(2), 25–35 (2002)
Matsutani, H., Koibuchi, M., Amano, H.: A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks. In: Proceedings of the International Conference on Parallel and Distributed Computing Systems, pp. 24–31 (2006)
Flich, J., Lopez, P., Malumbres, M.P., Duato, J.: Boosting the Performance of Myrinet Networks. IEEE Transactions on Parallel and Distributed Systems 13(7), 693–709 (2002)
Puente, V., Beivide, R., Gregorio, J.A., Prellezo, J.M., Duato, J., Izu, C.: Adaptive Bubble Router: A Design to Improve Performance in Torus Networks. In: Proceedings of the International Conference on Parallel Processing, pp. 58–67 (1999)
Dally, W.J., Towles, B.: Principles and Practices of Interconnection Networks. Morgan Kaufmann, San Francisco (2004)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Matsutani, H., Koibuchi, M., Amano, H. (2006). Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels. In: Guo, M., Yang, L.T., Di Martino, B., Zima, H.P., Dongarra, J., Tang, F. (eds) Parallel and Distributed Processing and Applications. ISPA 2006. Lecture Notes in Computer Science, vol 4330. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11946441_23
Download citation
DOI: https://doi.org/10.1007/11946441_23
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-68067-3
Online ISBN: 978-3-540-68070-3
eBook Packages: Computer ScienceComputer Science (R0)