Abstract
In this paper we present the architecture and implementation of a hardware NIC scheduler to guarantee QoS on servers for high speed LAN/SAN. Our proposal employs a programmable logic device based on an FPGA in order to store and update connection states, and to decide what data stream is to be sent next. The network architecture is connection-oriented and reliable, based on credit flow control. The architecture scales from 4 to 32 streams using a Xilinx Virtex 2000E. It supports links with speeds in the order of Gbps while, maintaining the delay and jitter constrains for the QoS streams.
This work was partially supported by the Spanish CICYT grant TIC2003-08154-C06 and the European FEDER program.
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Claver, J.M., Canseco, M., Agustí, P., León, G. (2006). A Hardware NIC Scheduler to Guarantee QoS on High Performance Servers. In: Guo, M., Yang, L.T., Di Martino, B., Zima, H.P., Dongarra, J., Tang, F. (eds) Parallel and Distributed Processing and Applications. ISPA 2006. Lecture Notes in Computer Science, vol 4330. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11946441_13
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DOI: https://doi.org/10.1007/11946441_13
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-68067-3
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