Abstract
On Chip Network (OCN) has been proposed as a new methodology for addressing the design challenges of future massly integrated system in nanoscale. In this paper, three differently heterogenous Tree-based network topologies are proposed as the OCN architectures for Video Object Plane Decoder (VOPD). The topologies are designed in order to maximize the system throughput. This paper also evaluates the proposed topologies by comparing them to other conventional topologies such as 2-D Mesh and Fat-Tree with respects to throughput, power consumption and size. We use the power modelling tool, known as Orion model to calculate the static powers, areas, and dynamic energies of three topologies. The experiment results show that our Tree-based topologies offer similar throughputs as Fat-Tree does and much higher throughputs compared to 2-D Mesh while use less chip areas and power consumptions.
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References
ITRS. International technology roadmap for semiconductors, edition (2005), http://public.itrs.net/
Benini, L., et al.: Networks On Chips: A new SoC paradigm. IEEE computer (January 2002)
Bertozzi, D., et al.: Network on Chip Design for Gigascale Systems on Chips. In: Zurawski, R. (ed.) Industrial Technology Handbook, pp. 49–80. CRC Press, Boca Raton (2004)
Guerrier, P., et al.: A generic architecture for on-chip packet-switched interconnectio. In: Proc. of Design Automation and Test in Europe Conf., pp. 250–256 (August 2000)
Kumar, S., et al.: A Network on Chip Architecture and Design Methodology. In: Proc of. Int’l Symp. VLSI, pp. 117–124 (2002)
Hu, J., et al.: Exploiting the Routing Flexibility for Energy Performance Aware Mapping of Regular NoC Architectures. In: Proc. of Design Automation and Test in Europe Conf. (March 2003)
Hu, J., et al.: Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time Constraints. In: Proc. of Design Automation and Test in Europe Conf. (February 2004)
Murali, S., et al.: Bandwidth-Constrained Mapping of Cores onto NoC Architectures. In: Proc. of International Conference on Design Automation and Test in Europe, pp. 896–901 (2004)
Hwang, H.S., et al.: Orion: A Power Performance Simulator for Interconnection Networks. IEEE Micro (November 2002)
Nguyen, H.-N., Ngo, V.-D., Choi, H.-W.: Realization of Video Object Plane Decoder on On-Chip Network Architecture. In: Yang, L.T., Zhou, X.-s., Zhao, W., Wu, Z., Zhu, Y., Lin, M. (eds.) ICESS 2005. LNCS, vol. 3820, pp. 256–264. Springer, Heidelberg (2005)
Dally, W.J., et al.: Route Packets, Not Wires: On Chip Interconnection Networks. In: DAC, pp. 684–689 (2001)
Ho, R., et al.: The future of wires. Proceedings of the IEEE 89(4), 490–504 (2001)
Dally, W.J., et al.: Route Packets, Not Wires: On-Chip Interconnection Networks. In: Proc of the 38th DAC (June 2001)
Vellanki, P., et al.: Quality-of-Service and Error Control Techniques for Network-on-Chip Architectures. In: Proceedings of the Great Lakes Symposium on VLSI (2004)
Eisley, N., et al.: High-level power analysis for on-chip networks. In: Proc of the 7th International Conference on Compilers, Architectures and Synthesis for Embedded Systems (September 2004)
Nurmi, J.: Network-on-Chip: A New Paradigm for System-on-Chip Design. In: Proc of International Symposium on System-on-Chip (November 2005)
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Ngo, VD., Nguyen, HN., Choi, HW. (2006). The Optimum Network on Chip Architectures for Video Object Plane Decoder Design. In: Guo, M., Yang, L.T., Di Martino, B., Zima, H.P., Dongarra, J., Tang, F. (eds) Parallel and Distributed Processing and Applications. ISPA 2006. Lecture Notes in Computer Science, vol 4330. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11946441_12
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DOI: https://doi.org/10.1007/11946441_12
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