Abstract
Current parallel architectures are not optimized to all different kinds of applications since they can vary in requirements and resource needs. An ideal system to attend different applications should be able to fit their different characteristics and resource needs and to improve application performance. Our objective is to design and to develop a system architecture that can be reconfigured to fulfill many kinds of the application requirements and run with a reduced communication overhead. Our main goal is a new Reconfigurable Chip-MultiProcessor architecture that improves adaptability to have better performance, regardless of the application requirements. Our results and its analysis show that our architecture provides greater flexibility and scalability and still obtains performance gain over one multiprocessor architecture. Our main contribution is a Reconfigurable Chip-Multiprocessor architecture, composed of reconfigurable processing, storage and interconnection elements.
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References
Burger, D., et al.: Scaling to the End of Silicon with EDGE Architectures Computer, vol. 37(7), pp. 44–55. IEEE Computer Society, Los Alamitos (2004)
Hammond, L., Basem, A.N., Olukotun, K.: A Single-Chip Multiprocessor. Computer Magazine 30(9), 79–85 (1997)
Compton, K., Hauck, S.: Reconfigurable Computing: A Survey of Systems and Software. ACM Computing Survey 34(2), 171–210 (2002)
Barroso, L.A., Gharachorloo, K., McNamara, R., Nowatzyk, A., Qadeer, S., Sano, B., Smith, S., Stets, R., Verghese, B.: Piranha: a scalable architecture based on sigle-chip multiprocessing. In: Proceedings of the 27th Annual International Symposium on Computer Architecture, pp. 282–293. IEEE Computer Society Press, Los Alamitos (2000)
Sang-Won, L., Yun-Seob, S., Soo-Won, K., Hyeong-Cheol, O., Woo-Jang, H.: Raptor: A single chip multiprocessor. In: The First IEEE Asia Pacific Conference on ASICs, pp. 217–220 (1999)
Nikitovic, M., Brorsson, M.: An adaptive chip-multiprocessor architecture for future mobile terminals. In: Proceedings of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2002), October 2003, pp. 43–49 (2003)
Ye, Z.A., Moshovos, A., Hauck, S., Banerjee, P.: CHIMAERA: A High-Performance Architecture With a Tightly-Coupled Reconfigurable Functional Unit. In: Proceedings of the 27th International Symposium on Computer Architecture, pp. 225–235 (2000)
Gottlieb, D.B., Cook, J.J., Walstrom, J.D., Ferrera, S., Wang, C.-W., Carter, N.P.: Clustered programmable-reconfigurable processors. In: Proceedings of the IEEE International Conference on Field Programmable Technology, December 2002, pp. 134–141 (2002)
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Boa, R.F., da Penha, D.O., Amaral, A.M., de Souza, M.O.S., da Silva Martins, C.A.P., Ekel, P.Y. (2006). RCMP: A Reconfigurable Chip-Multiprocessor Architecture. In: Min, G., Di Martino, B., Yang, L.T., Guo, M., Rünger, G. (eds) Frontiers of High Performance Computing and Networking – ISPA 2006 Workshops. ISPA 2006. Lecture Notes in Computer Science, vol 4331. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11942634_11
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DOI: https://doi.org/10.1007/11942634_11
Publisher Name: Springer, Berlin, Heidelberg
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