Skip to main content

Combining Offline and Online Optimizations: Register Allocation and Method Inlining

  • Conference paper
  • 371 Accesses

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 4279))

Abstract

Fast dynamic compilers trade code quality for short compilation time in order to balance application performance and startup time. This paper investigates the interplay of two of the most effective optimizations, register allocation and method inlining for such compilers. We present a bytecode representation which supports offline global register allocation, is suitable for fast code generation and verification, and yet is backward compatible with standard Java bytecode.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Amme, W., Dalton, N., von Ronne, J., Franz, M.: SafeTSA: A type safe and referentially secure mobile-code representation based on static single assignment form. In: Conference on Programming Language Design and Implementation (PLDI) (2001)

    Google Scholar 

  2. Azevedo, A., Nicolau, A., Hummel, J.: Java annotation-aware just-in-time (AJIT) compilation system. In: Java Grande Conference (1999)

    Google Scholar 

  3. Bernstein, D., Golumbic, M., Mansour, y., Pinter, R., Goldin, D., Krawczyk, H., Nahshon, I.: Spill code minimization techniques for optimizing compliers. In: Conference on Programming language design and implementation (PLDI) (1989)

    Google Scholar 

  4. Briggs, P., Cooper, K.D., Torczon, L.: Improvements to graph coloring register allocatoion. Transaction on Programming Languages and Systems (1994)

    Google Scholar 

  5. Callahan, D., Koblenz, B.: Register allocation via hierarchical graph coloring. In: Conference on Programming language design and implementation (PLDI) (1991)

    Google Scholar 

  6. Chaitin, G.J., Auslander, M.A., Chandra, A.K., Cocke, J., Hopkins, M.E., Markstein, P.W.: Register allocation via coloring. Journal of Computer Languages 6, 47–57 (1981)

    Article  Google Scholar 

  7. Standard Performance Evaluation Corporation. SPECjvm98 (1998)

    Google Scholar 

  8. Gupta, R., Soffa, M.L., Steele, T.: Register allocation via clique separators. In: Conference on Programming language design and implementation (PLDI) (1989)

    Google Scholar 

  9. Hummel, J., Azevedo, A., Kolson, D., Nicolau, A.: Annotating the Java bytecodes in support of optimization. Concurrency: Practice and Experience 9(11), 1003–1016 (1997)

    Article  Google Scholar 

  10. Jones, J., Kamin, S.: Annotating Java class files with virtual registers for performance. Concurrency: Practice and Experience 12(6), 389–406 (2000)

    Article  Google Scholar 

  11. Krintz, C., Calder, B.: Using annotations to reduce dynamic optimization time. In: Conference on Programming language design and implementation (PLDI) (2001)

    Google Scholar 

  12. Lee, H., von Dincklage, D., Diwan, A., Moss, J.E.B.: Understanding the behavior of compiler optimizations. Technical Report Technical Report CU-CS-978-04, University of Colorado at Boulder (2004)

    Google Scholar 

  13. Morrisett, G., Walker, D., Crary, K., Glew, N.: From system f to typed assembly language. In: Symposium on Principles of Programming Languages (POPL) (1998)

    Google Scholar 

  14. Pominville, P., Qian, F., Vallée-Rai, R., Hendren, L., Verbrugge, C.: A framework for optimizing java using attributes. In: Wilhelm, R. (ed.) CC 2001. LNCS, vol. 2027, p. 334. Springer, Heidelberg (2001)

    Chapter  Google Scholar 

  15. Rose, E., Rose, K.H.: Lightweight bytecode verification. In: Workshop Formal Underpinnings of the Java Paradigm (1998)

    Google Scholar 

  16. Shaylor, N.: A just-in-time compiler for memory-constrained low-power devices. In: Java Virtual Machine Research and Technology Symposium (JVM) (2002)

    Google Scholar 

  17. Shaylor, N., Simon, D.N., Bush, W.R.: A Java virtual machine architecture for very small devices. In: Conference on Language, compiler, and tool for embedded systems (LCTES) (2003)

    Google Scholar 

  18. Shi, Y., Gregg, D., Beatty, A., Ertl, M.A.: Virtual machine showdown: stack versus registers. In: Conference on Virtual execution environments (VEE) (2005)

    Google Scholar 

  19. Sites, R.L.: Machine-independent register allocation. In: Symposium on Programming Language Design and Implementation (1979)

    Google Scholar 

  20. Purdue University. The ovm virtual machine framework

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2006 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Yamauchi, H., Vitek, J. (2006). Combining Offline and Online Optimizations: Register Allocation and Method Inlining. In: Kobayashi, N. (eds) Programming Languages and Systems. APLAS 2006. Lecture Notes in Computer Science, vol 4279. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11924661_19

Download citation

  • DOI: https://doi.org/10.1007/11924661_19

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-48937-5

  • Online ISBN: 978-3-540-48938-2

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics