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Time Aware Modelling and Analysis of Multiclocked VLSI Systems

  • Tomi Westerlund
  • Juha Plosila
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4260)

Abstract

We introduce a formal, time aware framework for modelling and analysis multiclocked VLSI systems. We define a delay calculus framework for our timed formalism, and, furthermore, constraints with which to confine the correctness of the system under development, not only logically but also with respect to timing characteristics. We give an elaborate definition of the timed formalism, Timed Action Systems, and its delay models. With the timing aware formal development framework it is possible to obtain information of multiclocked VLSI systems already at high abstraction levels as our application, a GALS (globally asynchronous, locally synchronous) system, shows.

Keywords

Timed Action Systems GALS formal methods time 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Tomi Westerlund
    • 1
    • 2
  • Juha Plosila
    • 2
  1. 1.Turku Centre for Computer ScienceTurkuFinland
  2. 2.Department of Information Technology, Department of Information TechnologyUniversity of TurkuTurkuFinland

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