Abstract
In this work is presented an automated method for adjusting two-level cache memory hierarchy in order to reduce energy consumption in embedded applications. The proposed heuristic, TECH-CYCLES (Two-level Cache Exploration Heuristicconsidering CYCLES), consists of making a small search in the space of configurations of the two-level cache hierarchy, analyzing the impact of each parameter in terms of energy and number of cycles spent for a given application. Experiments show an average reduction of about 41% in the energy consumption by using our heuristic when compared with the existing heuristic (TCaT), also for two-level caches. Besides the energy improvement, this method also reduces the number of cycles needed to execute a given application by about 25%. In order to validate the proposed heuristic, twelve benchmarks from the MiBench suite have been used.
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References
Chang, H., Code, L., Hunt, M., Martin, G., McNelly, A.J., Todd, L.: Surviving the SOC revolution: A guide to platform-based design, 1st edn. Kluwer Academic Publishers, Dordrecht (1999)
Malik, B.M., Cermak, D.: A Low Power Unified Cache Architecture Providing Power and Performance Flexibility. In: Int. Symp. On Low Power Electronics and Design, June 2000, pp. 241–243 (2000)
Zhang, D., Vahid, F.: Cache configuration exploration on prototyping platforms. In: 14th IEEE Interational Workshop on Rapid System Prototyping, June 2003, p. 164 (2003)
Gordon-Ross, A., Vahid, F., Dutt, N.: Automatic Tuning of Two-Level Caches to Embedded Aplications. In: DATE, pp. 208–213 (February 2004)
Gordon-Ross, A., Vahid, F., Dutt, N.: Fast Configurable-Cache Tuning with a Unified Second-Level Cache. In: ISLPED 2005 (August 2005)
Givargis, T., Vahid, F.: Platune: A Tuning framework for system-on-a-chip platforms. IEEE Trans. Computer-Aided Design 21, 1–11 (2002)
Palesi, M., Givargis, T.: Multi-objective design space exploration using genetic algorithms. In: International Workshop on Hardware/Software Codesign (May 2002)
Silva-Filho, A.G., Lima, M.E.: A Heuristic for Energy Consumption Exploration Based on Two-Level Cache Hierarchy. In: Forum SoC 2005 (December 2005)
Silva-Filho, A.G., Lima, M.E., Nascimento, P.S.B., Eskinazi, R.: An Energy-Aware Exploration Approach Based on Open Software Enviroment. In: IESS 2005, July 2005, pp. 97–102 (2005)
Guttaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T., Brown, R.B.: Mibench: A free, commercially representative embedded benchmark suite. In: IEEE 4th Annual Workshop on Workload Characterization, pp. 1–12 (December 2001)
Dutt, N., Mamidipaka, M.: eCACTI: An Enhanced Power Estimation Model for On-chip Caches, TR 04-28 (september 2004)
Burger, D., Austin, T.M.: The SimpleScalar Tool Set, Version 2.0. Computer Architecture News 25(3), 13–25 (1997)
Shivakumar, P., Jouppi, N.P.: Cacti 3.0: An Integrated Cache Timing, Power and Area model, WRL Research Report 2001/2
Macii, E., Benini, L., Poncino, M.: Energy-Aware Design of Embedded Memories: A Survey of Technologies, Architectures and Optimization Techniques. ACM Transactions on Embedded Computing Systems 2(1), 5–32 (2003)
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Silva-Filho, A.G., Cordeiro, F.R., Sant’Anna, R.E., Lima, M.E. (2006). Heuristic for Two-Level Cache Hierarchy Exploration Considering Energy Consumption and Performance. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_8
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DOI: https://doi.org/10.1007/11847083_8
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