Abstract
We present a blackbox approach to model leakage currents of RTL data-path components. The model inputs are temperature, V DD , body voltage of NMOS and PMOS and the bitvector at the input. Additionally, the model accepts a statistical Gaussian variation introduced by intra-die and systematic variation introduced by inter-die. Both variations can be given independently for each BSIM-level process parameter; in this work we evaluate variation of channel length, gate-oxide thickness and channel doping. Model output is the sum of subthreshold, gate, and pn-junction leakage. The evaluation of an RT component can be done in milliseconds and the result for the 45nm and 65nm BPTM technology is within 2% against single BSIM4.40 evaluation and within 5% against statistical BSIM4.40 evaluation assuming 1% variation of the process parameters.
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Helms, D., Hoyer, M., Nebel, W. (2006). Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_6
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DOI: https://doi.org/10.1007/11847083_6
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-39094-7
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