Abstract
In this paper, an ABCD modeling approach is proposed to model the inductive and capacitive coupling effect between the interconnect lines in DSM circuits. Then, a physical aspect model is introduced to analyze the worst case crosstalk noise effect on the delay and rise time of the driver. It is observed that the inductive coupling effect can have a great effect on the timing characteristic of the interconnect line. Experimental results show that the method proposed in this paper differs from the HSPICE simulation with an average error less than 2.5% for both the 50% delay and the rise time.
This work was sponsored in party by NSFC under grand #90307016.
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References
Deutsch, A., et al.: When are Transmission Line Effects Important for On-Chip Interconnections? IEEE Transactions on Microwave Theory and Techniques 45, 1836–1846 (1997)
Sun, J., Zheng, Y., Ye, Q., Ye, T.: Worst-case crosstalk noise analysis based on dual-exponential noise metrics. In: Proc. VLSID 2005, pp. 348–353 (2005)
Ding, L., Blaauw, D., Mazumder, P.: Accurate crosstalk noise modeling for early signal integrity analysis. IEEE Trans. Computed-Aided Design of Integr. Circuits Syst. 22(5), 627–634 (2003)
Vittal, A., Marek-Sadowska, M.: Crosstalk reduction for VLSI. IEEE Trans. Computer-Aided Design of Integr. Circuits Syst. 16(3), 290–298 (1997)
Vittal, A., Chen, L.H., Marek-Sadowska, M., Wang, K.-P., Yang, S.: Crosstalk in VLSI interconnections. IEEE Trans. Computer-Aided Design of Integr. Circuits Syst. 18(12), 1817–1824 (1999)
Palit, A.K., Meyer, V., Anheier, W., Schloeffel, J.: ABCD modeling of crosstalk coupling noise to analyze the signal integrity losses on the victim interconnect in DSM chips. In: Proc. VLSID 2005, pp. 354–359 (2005)
Davis, J., Meindl, J.: Compact Distributed RLC Interconnect Models – Part II: Coupled Line Transient Expressions and Peak Crosstalk in Multilevel Networks. IEEE Trans. Electron Devices 47(11), 2078–2087 (2005)
Banerjee, K., Mehrotra, A.: Analysis of on-chip inductance effects for distributed RLC interconnects. IEEE Trans. Computer-Aided Design of Integr. Circuits Syst. 21(8), 904–915 (2002)
Lin, S., Yang, H.: A novel γd/n RLCG transmission line model considering complex RC(L) loads. IEEE Trans. Computer-Aided Design of Integr. Circuits Syst. (submitted, 2006)
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© 2006 Springer-Verlag Berlin Heidelberg
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Lin, S., Yang, H. (2006). Worst Case Crosstalk Noise Effect Analysis in DSM Circuits by ABCD Modeling. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_49
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DOI: https://doi.org/10.1007/11847083_49
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-39094-7
Online ISBN: 978-3-540-39097-8
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