Abstract
The aim of this study is to provide a multi level VHDL-AMS modeling of an analog Phase Locked Loop (PLL). Three model levels are described, analyzed and compared in terms of simulation CPU times and accuracy. The characteristic parameters of the PLL, such as the settling time, overshoot, voltage variations linked to charge pump architecture and final voltage are extracted from the intermediate level.
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References
Nicolle, B., et al.: VHDL-AMS modeling of a multistandard Phase Locked Loop. In: ICECS 2005 Proceeding, pp. 33–36 (2005)
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© 2006 Springer-Verlag Berlin Heidelberg
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Nicolle, B., Tatinian, W., Oudinot, J., Jacquemod, G. (2006). Hierarchical Modeling of a Fractional Phase Locked Loop. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_43
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DOI: https://doi.org/10.1007/11847083_43
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-39094-7
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