Abstract
Today and more tomorrow, electronic system design requires being concerned with the power issues. Currently, usual design tools consider the application power consumption after RTL synthesis. We propose in this article a FPGA design flow which integrates the power consideration at the early stages. Thus, the designer determines quickly the algorithm and architecture adequacy which respects the design specifications and the power budget.
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Elléouet, D., Savary, Y., Julien, N. (2006). An FPGA Power Aware Design Flow. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_40
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DOI: https://doi.org/10.1007/11847083_40
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-39094-7
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