Abstract
In this paper we present the effect of process variations on the design of clocked storage elements. This work proposes to use the Energy-Delay space analysis for a true representation of the design trade-offs. Consequently, this work also shows a comparison of clocked storage elements under a specific set of system constraints for typical corner design and high yield corner design. Finally, we show that designing for high yield can affect the choice of topology in order to achieve energy efficiency.
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Giacomotto, C., Nedovic, N., Oklobdzija, V.G. (2006). Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_35
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DOI: https://doi.org/10.1007/11847083_35
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-39094-7
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