Modeling of Crosstalk Fault in Defective Interconnects

Abstract

The manufacturing defect in the interconnect lines can lead to various electrical faults, e.g. defect due to under-etching effect/conductive particle contamination on interconnect line can lead to increased coupling capacitances between the two adjacent interconnects, which, in turn, can eventually result in crosstalk fault in the DSM chips. In this paper we describe the line defect-based-crosstalk fault model that will be helpful in analyzing the severity of the defect/fault, as the crosstalk fault occasionally leads to various signal integrity losses, such as timing violation due to excessive signal delay or speed-up, logic failure due to crosstalk positive/negative glitch above/below logic low/high threshold and also reliability problem particularly due to crosstalk glitch above logic high threshold. Our crosstalk fault model accuracy is very close to PSPICE simulation results when the defect/fault is located in the middle of interconnects, whereas for the defects located at the near-end/far-end side of aggressor-victim the model accuracy differs approximately by ±5% respectively.

CMOS12 technology data provided by Philips Semiconductors GmbH, DTC, Hamburg, Germany.