Abstract
This paper evaluates the feasibility of on-chip transmission-line interconnect at 45nm CMOS technology. Circuit performances tend to depend heavily on global interconnects, and power and delay of global interconnects are increased due to the miniaturization of process technology. On-chip transmission line has been proposed, which can improve such the large delay and large power consumption of the long RC interconnects. The improvement has been evaluated only for a single interconnect. In this paper, the total power reduction of the entire circuit is evaluated for 45nm technology, which is based on the measurement results at 180nm technology. As an example, the power consumption of global interconnects is improved by 6.6% on a circuit designed for 45nm process.
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© 2006 Springer-Verlag Berlin Heidelberg
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Okada, K., Uezono, T., Masu, K. (2006). Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_18
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DOI: https://doi.org/10.1007/11847083_18
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-39094-7
Online ISBN: 978-3-540-39097-8
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