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Towards an Optimal Implementation of MLP in FPGA

  • E. M. Ortigosa
  • A. Cañas
  • R. Rodríguez
  • J. Díaz
  • S. Mota
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3985)

Abstract

We present the hardware implementation of partially connected neural network that is defined as an extended of the Multi-Layer Perceptron (MLP) model. We demonstrate that partially connected neural networks lead to a higher performance in terms of computing speed (requiring less memory and computing resources). This work addresses a complete study that compares the hardware implementation of MLP and a partially connected version (XMLP) in terms of computing speed, hardware resources and performance cost. Furthermore, we study also different memory management strategies for the connectivity patterns.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • E. M. Ortigosa
    • 1
  • A. Cañas
    • 1
  • R. Rodríguez
    • 1
  • J. Díaz
    • 1
  • S. Mota
    • 2
  1. 1.Dept. of Computer Architecture and TechnologyUniversity of GranadaGranadaSpain
  2. 2.Dept. of Informatics and Numerical AnalysisUniversity of CórdobaCórdobaSpain

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