FPGA Implementation of a GF(2m) Tate Pairing Architecture

  • Maurice Keller
  • Tim Kerins
  • Francis Crowe
  • William Marnane
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3985)


This paper presents a hardware implementation of a dual mode Tate pairing/elliptic curve processor over fields of characteristic 2. The architecture can be reconfigured for different underlying field sizes and hence can support different security levels. The processor also performs elliptic curve point scalar multiplication. The performance of the architecture implemented on an FPGA is evaluated for various security levels.


Elliptic Curve Clock Cycle Hardware Implementation Security Level FPGA Implementation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Dutta, R., Barua, R., Sarkar, P.: Pairing-Based Cryptographic Protocols: A Survey. Cryptology ePrint Archive, Report 064/2004 (2004)Google Scholar
  2. 2.
    Boneh, D., Franklin, M.: Identity Based Encryption from the Weil Pairing. SIAM J. of Computing 32(3), 586–615 (2003)MathSciNetCrossRefzbMATHGoogle Scholar
  3. 3.
    Zhao, M., Smith, S.W., Nicol, D.M.: Aggregated Path Authentication for Efficient BGP Security. In: Proc. 12th ACM Conference on Computer and Communications Security, pp. 128–138 (November 2005)Google Scholar
  4. 4.
    Barreto, P.S.L.M., Kim, H.Y., Lynn, B., Scott, M.: Efficient Algorithms for Pairing-Based Cryptosystems. In: Yung, M. (ed.) CRYPTO 2002. LNCS, vol. 2442, pp. 354–368. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  5. 5.
    Galbraith, S.D., Harrison, K., Soldera, D.: Implementing the Tate Pairing. In: Proc. Fifth Algorithmic Number Theory Symp (ANTS-V), pp. 324–337 (2002)Google Scholar
  6. 6.
    Duursma, I., Lee, H.-S.: Tate Pairing Implementation for Hyperelliptic Curves y 2 = x p − x + d. In: Laih, C.-S. (ed.) ASIACRYPT 2003. LNCS, vol. 2894, pp. 111–123. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  7. 7.
    Barreto, P.S.L.M., Galbraith, S., O’hEigeartaigh, C., Scott, M.: Efficient Pairing Computation on Supersingular Abelian Varieties. Cryptology ePrint Archive, Report 375/2004 (2004)Google Scholar
  8. 8.
  9. 9.
    Kerins, T., Marnane, W.P., Popovici, E.M., Barreto, P.S.L.M.: Hardware Accelerators for Pairing Based Cryptosystems. In: IEE Proceedings on Information Security, vol. 155(1), pp. 47–56 (October 2005)Google Scholar
  10. 10.
    Ronan, R., O’hEigeartaigh, C., Murphy, C., Scott, M., Kerins, T., Marnane, W.P.: A Dedicated Processor for the eta Pairing. Cryptology ePrint Archive, Report 330/2005 (2005)Google Scholar
  11. 11.
    Knuth, D.: The Art of Computer Programming: Seminumerical Algorithms, 2nd edn., vol. 2. Addison-Wesley, Reading (1981)zbMATHGoogle Scholar
  12. 12.
    Song, L., Parhi, K.: Low Energy Digit-Serial/Parallel Finite Field Multipliers. Kulwer Journal of VLSI Signal Processing Systems 19(2), 149–166 (1998)CrossRefGoogle Scholar
  13. 13.
    Shantz, S.C.: From Euclid’s GCD to Montgomery Multiplication to the Great Divide. TR-2001-95, Technical Report, Sun Microsystems (2001)Google Scholar
  14. 14.
    Karatsuba, A., Ofman, Y.: Multiplication on Many-Digital Numbers by Automatic Computers. Translation in Physics-Doklady 7, 595–596 (1963)Google Scholar
  15. 15.
    Keller, M., Kerins, T., Marnane, W.: FPGA Implementation of a GF(24m) Multiplier for use in Pairing Based Cryptosystems. In: Proc. International Conference on Field Programmable Logic and Applications 2005, pp. 594–597 (August 2005)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Maurice Keller
    • 1
  • Tim Kerins
    • 1
  • Francis Crowe
    • 1
  • William Marnane
    • 1
  1. 1.Dept. of Electrical and Electronic EngineeringUniversity College CorkCork CityIreland

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