A New Approach to Assess Defragmentation Strategies in Dynamically Reconfigurable FPGAs

  • Manuel G. Gericota
  • Gustavo R. Alves
  • Luís F. Lemos
  • José M. Ferreira
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3985)


Fragmentation on dynamically reconfigurable FPGAs is a major obstacle to the efficient management of the logic space in reconfigurable systems. When resource allocation decisions have to be made at run-time a rearrangement may be necessary to release enough contiguous resources to implement incoming functions. The feasibility of run-time relocation depends on the processing time required to set up rearrangements. Moreover, the performance of the relocated functions should not be affected by this process or otherwise the whole system performance, and even its operation, may be at risk.

Relocation should take into account not only specific functional issues, but also the FPGA architecture, since these two aspects are normally intertwined. A simple and fast method to assess performance degradation of a function during relocation and to speed up the defragmentation process, based on previous function labelling and on the application of the Euclidian distance concept, is proposed in this paper.


Performance Degradation Field Programmable Gate Array Propagation Delay Logic Space Proximity Factor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Manuel G. Gericota
    • 1
  • Gustavo R. Alves
    • 1
  • Luís F. Lemos
    • 1
  • José M. Ferreira
    • 2
  1. 1.Department of Electrical Engineering – ISEPRua Dr. António Bernardino de AlmeidaPortoPortugal
  2. 2.Department of Electrical and Computer Engineering – FEUPRua Dr. Roberto FriasPortoPortugal

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