A Reconfigurable Data Cache for Adaptive Processors

  • D. Benitez
  • J. C. Moure
  • D. I. Rexachs
  • E. Luque
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3985)


Adaptive processors can exploit the different characteristics exhibited by program phases better than a fixed hardware. However, they may significantly degrade performance and/or energy consumption. In this paper, we describe a reconfigurable cache memory, which is efficiently applied to the L1 data cache of an embedded general-purpose processor. A realistic hardware/software methodology of run-time tuning and reconfiguration of the cache is also proposed, which is based on a pattern-matching algorithm. It is used to identify the cache configuration and processor frequency when the programs data working-set changes. Considering a design scenario driven by the best product execution time×energy consumption, we show that power dissipation and energy consumption of a two-level cache hierarchy and the product time×energy can be reduced on average by 39%, 38% and 37% respectively, when compared with a non-adaptive embedded microarchitecture.


Power Dissipation Chip Area Data Cache Cache Memory Learn Stage 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • D. Benitez
    • 1
  • J. C. Moure
    • 2
  • D. I. Rexachs
    • 2
  • E. Luque
    • 2
  1. 1.IUSIANI and DIS DepartmentUniversity of Las Palmas G.C.Las PalmasSpain
  2. 2.Computer Architecture and Operating System DepartmentUniversitat Autonoma BarcelonaBarcelonaSpain

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