Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support

  • Nikolaos Vassiliadis
  • George Theodoridis
  • Spiridon Nikolaidis
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3985)


A previously proposed Reconfigurable Instruction Set Processor (RISP) architecture, which tightly couples a coarse-grain Reconfigurable Functional Unit (RFU) to a RISC processor, is considered. Two architectural enhancements, namely partial predicated execution and virtual opcode are presented. An automated development framework for the introduced architecture is proposed. In order to evaluate both the architecture and the development framework a complete MPEG-2 encoder application is used. The efficiency of the predicated execution is proved and impressive speedup of the application is produced. Also, the use of virtual opcode to alleviate the opcode space explosion is demonstrated.


Basic Block Partial Predication Target Architecture Execution Cycle Instruction Level Parallelism 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Nikolaos Vassiliadis
    • 1
  • George Theodoridis
    • 1
  • Spiridon Nikolaidis
    • 1
  1. 1.Section of Electronics and Computers, Department of PhysicsAristotle University of ThessalonikiThessalonikiGreece

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