Area/Performance Improvement of NoC Architectures

  • Mário P. Véstias
  • Horácio C. Neto
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3985)


The design of electronic systems in a System-on-Chip (SoC) depends on the reliable and efficient interconnection of many different components. The Network-on-Chip (NoC) has emerged as a scalable communication infrastructure with high bandwidth able to tackle the communication needs of future SoC. In this paper, we present a generic NoC architecture that can be customized to the specific communication needs of an application in order to reduce the area with minimal degradation of the latency of the system.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Mário P. Véstias
    • 1
  • Horácio C. Neto
    • 2
  1. 1.ISEL/INESC-IDPortugal
  2. 2.INESC-IDPortugal

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