Implementation of LPM Address Generators on FPGAs

  • Hui Qin
  • Tsutomu Sasao
  • Jon T. Butler
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3985)


We propose the multiple LUT cascade as a means to configure an n-input LPM (Longest Prefix Match) address generator commonly used in routers to determine the output port given an address. The LPM address generator accepts n-bit addresses which it matches against k stored prefixes. We implement our design on a Xilinx Spartan-3 FPGA for n = 32 and k = 504 ~511. Also, we compare our design to a Xilinx proprietary TCAM (ternary content-addressable memory) design and to another design we propose as a likely solution to this problem. Our best multiple LUT cascade implementation has 5.20 times more throughput, 31.71 times more throughput/area and is 2.89 times more efficient in terms of area-delay product than Xilinx’s proprietary design. Furthermore, its area is only 19% of Xilinx’s design.


Address Generator Special Encoder Address Line Priority Encoder Ternary Vector 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Hui Qin
    • 1
  • Tsutomu Sasao
    • 1
  • Jon T. Butler
    • 2
  1. 1.Department of Computer Science and ElectronicsKyushu Institute of TechnologyFukuokaJapan
  2. 2.Department of Electrical and Computer EngineeringNaval Postgraduate SchoolMontereyUSA

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