Abstract
In this paper an architecture based on FPGA’s for real time image processing is described. The system is composed of a high resolution (1280×1024) CMOS sensor connected to a FPGA that will be in charge of acquiring images from the sensor and controlling it too. A PC sends certain orders and parameters, configured by the user, to the FPGA. The connexion between the PC and the FPGA is made through the parallel port. On the other hand, the resolution of the captured image, as well as the selection of a window of interest inside the image, are configured by the user in the PC. Finally, a system to make the convolution between the captured image and a nxn-mask is shown.
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Datasheets 1.3 Megapixel CMOS Active pixel digital image sensor: MT9M413
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© 2006 Springer-Verlag Berlin Heidelberg
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Bravo, I., Jiménez, P., Mazo, M., Lázaro, J.L., Martín, E. (2006). Architecture Based on FPGA’s for Real-Time Image Processing. In: Bertels, K., Cardoso, J.M.P., Vassiliadis, S. (eds) Reconfigurable Computing: Architectures and Applications. ARC 2006. Lecture Notes in Computer Science, vol 3985. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11802839_21
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DOI: https://doi.org/10.1007/11802839_21
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-36708-6
Online ISBN: 978-3-540-36863-2
eBook Packages: Computer ScienceComputer Science (R0)