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Handel-C Design Enhancement for FPGA-Based DV Decoder

  • Sławomir Cichoń
  • Marek Gorgoń
  • Mirosław Pac
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3985)

Abstract

In the paper the authors present an implementation of the algorithm of DV Decoder conformant to IEC-61834-2 standard in reprogrammable resources . A software implementation has been realized and then transferred to the Handel-C language. By parallelization of the algorithm and using language mechanisms in Handel-C the processing efficiency has been increased 10 times with respect to the initial hardware implementation. The implementation has been verified in hardware-software environment with real data transmitted on-line from a DV camcorder.

Keywords

Parallel algorithm high level languages video decompression field programmable gate array 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Sławomir Cichoń
    • 1
  • Marek Gorgoń
    • 1
  • Mirosław Pac
    • 1
  1. 1.Biocybernetic Laboratory, Department of AutomaticsAGH University of Science and TechnologyKrakówPoland

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