Handel-C Design Enhancement for FPGA-Based DV Decoder

  • Sławomir Cichoń
  • Marek Gorgoń
  • Mirosław Pac
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3985)


In the paper the authors present an implementation of the algorithm of DV Decoder conformant to IEC-61834-2 standard in reprogrammable resources . A software implementation has been realized and then transferred to the Handel-C language. By parallelization of the algorithm and using language mechanisms in Handel-C the processing efficiency has been increased 10 times with respect to the initial hardware implementation. The implementation has been verified in hardware-software environment with real data transmitted on-line from a DV camcorder.


Parallel algorithm high level languages video decompression field programmable gate array 


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  1. 1.
    IEC 61834-2 (1998-08) Recording - Helical-scan digital video cassette recording system using 6.3 mm magnetic tape for consumer use (525-60, 62550, 1125-60 and 1250-50 systems), IEC (1998)Google Scholar
  2. 2.
    IEEE Std. 1394-1995 IEEE Standard for a High Performance Serial Bus. IEEE (1995)Google Scholar
  3. 3.
    Dhir, A.: IEEE 1394 and HAVi Are the Leading Technologies for Wired Home Networking. Xcell Journal 43, 48–51 (2002)Google Scholar
  4. 4.
    Divio and Xilinx Collaborate to deliver next-generation DV codec and decoder reference design, On-line:
  5. 5.
    Merlin 2003 DV and MPEG-2 recorder and Dual Stream Decoder, Users Manual, Skymicro Inc. (2003), On-line:
  6. 6.
    Richardson, I.E.G.: Video Codec Design, 1st edn. John Wiley & Sons, Chichester (2002)CrossRefGoogle Scholar
  7. 7.
    Loeffler, C., Ligtenberg, A., Moschytz, G.S.: Practical Fast 1-DCT Algorithms with 11 Multiplications. In: Proc. of the International Conference on Acoustics, Speech, and Signal Processing, pp. 988–991. IEEE, Los Alamitos (1989)CrossRefGoogle Scholar
  8. 8.
    van Eijndhoven, J., Sijstermans, F.: Data Processing Device and method of Computing the Cosine Transform of a Matrix. PCT Patent No, WO 9948025 (1999)Google Scholar
  9. 9.
    Nikara, J., Vassiliadis, S., Takala, J., Sima, M., Liuha, P.: Parallel Multiple-Symbol Variable-Length Decoding. In: Proceedings of ICCD - VLSI in Computers and Processors, pp. 126–131. IEEE, Los Alamitos (2002)Google Scholar
  10. 10.
    Wiatr, K., Jamro, E.: Implementation of Multipliers in FPGA Structures. In: Proc. of IEEE International Symposium on Quality Electronic Design, pp. 415–420. IEEE Computer Society, Los Alamitos (2001)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Sławomir Cichoń
    • 1
  • Marek Gorgoń
    • 1
  • Mirosław Pac
    • 1
  1. 1.Biocybernetic Laboratory, Department of AutomaticsAGH University of Science and TechnologyKrakówPoland

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