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Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor

  • Vu Manh Tuan
  • Yohei Hasegawa
  • Naohiro Katsura
  • Hideharu Amano
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3985)

Abstract

The Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor with the capability of changing its hardware functionality within a clock cycle. While implementing an application on the DRP, designers face the task of selecting how to efficiently use resources in order to achieve particular goals such as to improve the performance, to reduce the power dissipation, or to minimize the resource use. To analyze the impact of trade-off selections on these aspects, the Discrete Cosine Transform (DCT) algorithm has been implemented exploiting various design policies. The evaluation result shows that the performance, cost and consuming power are influenced by the implementation method. For example, the execution time can reduce 17% in case of using the distributed memory against the register files; or up to 40% whether the embedded multipliers are used.

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References

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    Motomura, M.: A Dynamically Reconfigurable Processor Architecture. In: Microprocessor Forum (October 2002)Google Scholar
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    Suzuki, M., Hasegawa, Y., Yamada, Y., Kaneko, N., Deguchi, K., Amano, H., Anjo, K., Motomura, M., Wakabayashi, K., Toi, T., Awashima, T.: Stream Applications on the Dynamically Reconfigurable Processor. In: Proceedings of International Conference on Field Programmable Technology (FPT 2004), pp. 137–144 (December 2004)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Vu Manh Tuan
    • 1
  • Yohei Hasegawa
    • 1
  • Naohiro Katsura
    • 1
  • Hideharu Amano
    • 1
  1. 1.Graduate School of Science and TechnologyKeio UniversityKanagawaJapan

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