Rescheduling for Optimized SHA-1 Calculation

  • Ricardo Chaves
  • Georgi Kuzmanov
  • Leonel Sousa
  • Stamatis Vassiliadis
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4017)


This paper proposes the rescheduling of the SHA-1 hash function operations on hardware implementations. The proposal is mapped on the Xilinx Virtex II Pro technology. The proposed rescheduling allows for a manipulation of the critical path in the SHA-1 function computation, facilitating the implementation of a more parallelized structure without an increase on the required hardware resources. Two cores have been developed, one that uses a constant initialization vector and a second one that allows for different Initialization Vectors (IV), in order to be used in HMAC and in the processing of fragmented messages. A hybrid software/hardware implementation is also proposed. Experimental results indicate a throughput of 1.4 Gbits/s requiring only 533 slices for a constant IV and 596 for an imputable IV. Comparisons to SHA-1 related art suggest improvements of the throughput/slice metric of 29% against the most recent commercial cores and 59% to the current academia proposals.


Hash Function Critical Path Data Block Initialization Vector Input Message 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Ricardo Chaves
    • 1
    • 2
  • Georgi Kuzmanov
    • 2
  • Leonel Sousa
    • 1
  • Stamatis Vassiliadis
    • 2
  1. 1.Instituto Superior TécnicoINESC-IDLisbonPortugal
  2. 2.Computer Engineering LabTUDelftDelftThe Netherlands

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