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CARROT – A Tool for Fast and Accurate Soft Error Rate Estimation

  • Dimitrios Bountas
  • Georgios I. Stamoulis
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4017)

Abstract

We present a soft error rate (SER) analysis methodology within a simulation and design environment that covers a broad spectrum of design problems and parameters. Our approach includes modeling of the particle hit at the transistor level, fast Monte-Carlo type simulation to obtain the latching probability of a particle hit on all nodes of the circuit, embedded timing analysis to obtain the latching window, and fine-grained accounting of the electrical masking effects to account for both the effects of scaling and of pulse duration versus the period of the system clock to get an estimate of the maximum SER of the circuit. This approach has been implemented in CARROT and placed under a broad design environment to assess design tradeoffs with SER as a parameter.

Keywords

SER combinational circuits simulation 

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References

  1. 1.
    International technology roadmap for semiconductors (2002), http://public.itrs.net/
  2. 2.
    Murley, P.C., Srinivasan, G.R.: Soft-error Monte Carlo modeling program, SEMM. IBM Journal of Research and Development 40(1), 109–118 (1996)CrossRefGoogle Scholar
  3. 3.
    Yang, F.L., Saleh, R.A.: Simulation and analysis of transient faults in digital circuits. IEEE Journal of Solid-State Circuits 27(3), 258–264 (1992)CrossRefGoogle Scholar
  4. 4.
    Zhang, M., Shanbhag, N.R.: A soft error rate analysis (SERA) methodology. In: Proceedings of International Conference on Computer Aided Design, pp. 111–118 (2004)Google Scholar
  5. 5.
    Baze, M.P., Buchner, S.P., Bartholet, W.G., Dao, T.A.: An SEU analysis approach for error propagation in digital VLSI CMOS ASICs. IEEE Transactions on Nuclear Science 42(6), 1863–1869 (1995)CrossRefGoogle Scholar
  6. 6.
    Cha, H., Rudnick, E.M., Patel, J.H., Iyer, R.K., Choi, G.S.: A gate-level simulation environment for alpha-particle-induced transient faults. IEEE Transactions on Computers 45(11), 1248–1256 (1996)zbMATHCrossRefGoogle Scholar
  7. 7.
    Dhillon, Y.S., Diril, A.U., Chatterjee, A.: Soft-error tolerance analysis and optimization of nanometer circuits. In: Proceedings of Design, Automation, and Test in Europe, pp. 288–293 (2005)Google Scholar
  8. 8.
    Zhao, C., Bai, X., Dey, S.: A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits. In: Proceedings of Design Automation Conference, pp. 894–899 (2004)Google Scholar
  9. 9.
    Lantz, L.: Soft errors induced by alpha particles. IEEE Transaction on Reliability 45(2), 174–179 (1996)CrossRefGoogle Scholar
  10. 10.
    Messenger, G.C.: Collection of charge on junction nodes from ion tracks. IEEE Trans. Nucl. Sci. NS-29(6), 2024–2031 (1982)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Dimitrios Bountas
    • 1
  • Georgios I. Stamoulis
    • 1
  1. 1.Department of Computer and Communications EngineeringUniversity of ThessalyVolosGreece

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