Memory Architecture Evaluation for Video Encoding on Enhanced Embedded Processors

  • Ali Iranpour
  • Krzysztof Kuchcinski
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4017)


In this paper we investigate the impact of different memory configurations on performance and energy consumption of the video encoding applications, MPEG-4 and H.264. The memory architecture is integrated with SIMD extended embedded processor, proposed in our previous work. We explore both dedicated memories and multilevel cache architectures and perform exhaustive simulations. The simulations have been conducted using highly optimized proprietary video encoding code for mobile handheld devices. Our simulation results show that the performance improvement of dedicated memories on video encoding applications is not very significant. The multilevel cache-based architecture processes approximately 17 frames/s compared to 19-22 frames/s for 512 KB dedicated on-chip zero-wait state memory. Thus it is difficult to justify using dedicated memory for this kind of embedded systems, when energy consumption and cost of implementation are also considered.


Discrete Cosine Transform Cache Size Data Cache Memory Architecture Embed Processor 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Ali Iranpour
    • 1
  • Krzysztof Kuchcinski
    • 1
  1. 1.Department of Computer ScienceLund UniversityLundSweden

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