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Integrated Instruction Scheduling and Fine-Grain Register Allocation for Embedded Processors

  • Dae-Hwan Kim
  • Hyuk-Jae Lee
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4017)

Abstract

This paper proposes a new integration technique, called IRIS (Integrated Register allocation and Instruction Scheduling), to combine instruction scheduling and register allocation. Both register allocation and instruction scheduling are performed simultaneously at each variable reference where the selection between serialization by scheduling and spilling by register allocation is determined. To make a right selection, the costs of serialization and spilling are estimated with a cost model proposed to reduce the complexity of the estimation. Experiments show that IRIS achieves significant improvements when compared to widely-used existing techniques.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Dae-Hwan Kim
    • 1
  • Hyuk-Jae Lee
    • 1
  1. 1.School of Electrical Engineering and Computer ScienceSeoul National UniversitySeoulKorea

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