Integrated Instruction Scheduling and Fine-Grain Register Allocation for Embedded Processors
This paper proposes a new integration technique, called IRIS (Integrated Register allocation and Instruction Scheduling), to combine instruction scheduling and register allocation. Both register allocation and instruction scheduling are performed simultaneously at each variable reference where the selection between serialization by scheduling and spilling by register allocation is determined. To make a right selection, the costs of serialization and spilling are estimated with a cost model proposed to reduce the complexity of the estimation. Experiments show that IRIS achieves significant improvements when compared to widely-used existing techniques.
Unable to display preview. Download preview PDF.
- 2.Briggs, P., Cooper, K.D., Kennedy, K., Torczon, L.: Coloring heuristics for register allocation. In: Proceedings of ACM PLDI 1989, pp. 275–284 (1989)Google Scholar
- 3.Fraser, C.W., Hanson, D.R.: A Retargetable C Compiler: Design and Implementation. Benjamin/Cummings (1995)Google Scholar
- 4.Gibbons, P.B., Muchnick, S.S.: Efficient instruction scheduling for a pipelined architecture. In: Proceedings of CC 1986, pp. 11–16 (1986)Google Scholar
- 5.Goodman, J.R., Hsu, W.C.: Code scheduling and register allocation in large basic blocks. In: Proceedings of Supercomputing 1988, pp. 442–452 (1988)Google Scholar
- 7.Muchnick, S.S.: Advanced compiler design and implementation. Morgan Kaufmann, SanFrancisco (1997)Google Scholar
- 8.Norris, C., Pollock, L.L.: An experimental study of several cooperative register allocation and instruction scheduling strategies. In: Proceedings of MICRO 1995, pp. 169–179 (1995)Google Scholar
- 9.Pinter, S.: Register allocation with instruction scheduling: A new approach. In: Proceedings of ACM PLDI 1993, pp. 248–257 (1993)Google Scholar