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Automatic Test Pattern Generation

  • Conference paper
Formal Methods for Hardware Verification (SFM 2006)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 3965))

Abstract

The postproduction test of integrated circuits is crucial to ensure a high quality of the final product. This test is carried out by checking the correct response of the chip under predefined input stimuli – or test patterns. These patterns are calculated by algorithms for Automatic Test Pattern Generation (ATPG).

The basic concepts and algorithms for ATPG are reviewed in this chapter. Then, an advanced SAT-based ATPG tool is introduced and emprically evaluated.

This work was supported in part by DFG grant DR 287/15-1.

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Author information

Authors and Affiliations

  1. Institute of Computer Science, University of Bremen, 28359, Bremen, Germany

    Rolf Drechsler & Görschwin Fey

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  1. Rolf Drechsler
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  2. Görschwin Fey
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Editors and Affiliations

  1. Istituto di Scienze e Tecnologie dell’Informazione, Università di Urbino “Carlo Bo”, Italy

    Marco Bernardo

  2. FBK-IRST, Povo, Trento, Italy

    Alessandro Cimatti

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© 2006 Springer-Verlag Berlin Heidelberg

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Drechsler, R., Fey, G. (2006). Automatic Test Pattern Generation. In: Bernardo, M., Cimatti, A. (eds) Formal Methods for Hardware Verification. SFM 2006. Lecture Notes in Computer Science, vol 3965. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11757283_2

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  • DOI: https://doi.org/10.1007/11757283_2

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-34304-2

  • Online ISBN: 978-3-540-34305-9

  • eBook Packages: Computer ScienceComputer Science (R0)

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