Skip to main content
SpringerLink
Log in

Computer Assisted Source-Code Parallelisation

  • Conference paper
Computational Science and Its Applications - ICCSA 2006 (ICCSA 2006)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 3984))

Included in the following conference series:

Abstract

Many single-processor embedded systems are implemented using a time-triggered co-operative (TTC) scheduler. When considering possible alternatives to such a design, one option is a multi-CPU architecture, created using off-the-shelf processors or SoC techniques. In order to allow the rapid assessment of such design alternatives, we are exploring ways in which single-processor TTC code may be “automatically” converted to a multi-CPU equivalent. In this paper, we discuss the design of a prototype source code conversion tool. The input to this tool is the source code for the tasks of a single processor system using a TTC scheduler. The output from the tool (in the current version) is the equivalent multi-processor code based on either a “domino” scheduler or a shared-clock scheduler. In order to assess the effectiveness of the tool, we have used it it in a non-trivial case study: the results from this study are presented in detail.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Kopetz, H.: Real-Time Systems: Design Principles for Distributed Embedded Applications. Kluwer Academic, Dordrecht (1997)

    MATH  Google Scholar 

  2. Siemers, C., Falsett, R., Seyer, R., Ecker, K.: Reliable event-triggered systems for mechatronic applications. Journal of Systems and Software 77, 17–26 (2005)

    Article  Google Scholar 

  3. Allworth, S.T.: Introduction to Real-Time Software Design. Macmillan, Basingstoke (1981)

    Google Scholar 

  4. Nissanke, N.: Realtime Systems. Prentice-Hall, Englewood Cliffs (1997)

    Google Scholar 

  5. Pont, M.J.: Patterns for Time-Triggered Embedded Systems. Addison-Wesley, Reading (2001)

    Google Scholar 

  6. Storey, N.: Safety-Critical Computer Systems. Addison-Wesley, Reading (1996)

    Google Scholar 

  7. Bate, I.J.: Introduction to scheduling and timing analysis. In: The Use of Ada in Real-Time Systems, IEE Conference Publication 00/034 (2000)

    Google Scholar 

  8. Ward, N.J.: The static analysis of a safety-critical avionics control system. In: Air Transport Safety: Proceedings of the Safety and Reliability Society Spring Conference, SaRS, Ltd (1991)

    Google Scholar 

  9. Baker, T.P., Shaw, A.: The cyclic executive model and ada. Real-Time Systems 1(1), 7–25 (1989)

    Article  Google Scholar 

  10. Locke, C.D.: Software architecture for hard real-time applications: Cyclic executives vs. fixed priority executives. Real-Time Systems 4(1), 37–53 (1992)

    Article  Google Scholar 

  11. Pont, M.J.: Embedded C. Addison-Wesley, Reading (2002)

    Google Scholar 

  12. Ayavoo, D., Pont, M.J., Parker, S.: Using simulation to support the design of distributed embedded control systems: A case study. In: Koelmans, A., Bystrov, A., Pont, M. (eds.) Proceedings of the 1st UK Embedded Forum, University of Newcastle upon Tyne, pp. 54–65 (2004)

    Google Scholar 

  13. Phatrapornnant, T., Pont, M.J.: Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling. IEEE Transactions on Computers 55(2), 113–124 (2006)

    Article  Google Scholar 

  14. Edwards, T., Pont, M.J., Scotson, P., Crumpler, S.: A test-bed for evaluating and comparing designs for embedded control systems. In: Koelmans, A., Bystrov, A., Pont, M. (eds.) Proceedings of the 1st UK Embedded Forum, University of Newcastle upon Tyne, pp. 106–126 (2004)

    Google Scholar 

  15. Key, S., Pont, M.J.: Implementing PID control systems using resource-limited embedded processors. In: Koelmans, A., Bystrov, A., Pont, M. (eds.) Proceedings of the 1st UK Embedded Forum, University of Newcastle upon Tyne, pp. 76–92 (2004)

    Google Scholar 

  16. Bate, I.J.: An Architecture for Distributed Real-Time Systems. University of York, Department of Computer Science, University Technology Centre, UTC (1997)

    Google Scholar 

  17. Maaita, A., Pont, M.J.: Using ‘planned pre-emption’ to reduce levels of task jitter in a time-triggered hybrid scheduler. In: Proceedings of the 2nd UK Embedded Forum (2005)

    Google Scholar 

  18. Lysecky, R., Vahid, F.: A study of the speedups and competitiveness of FPGA soft processor cores using dynamic hardware/software partitioning. In: Proceedings of the European Conference on Design, Automation and Test (DATE), Munich, Germany, pp. 18–23. IEEE Computer Society, Los Alamitos (2005)

    Google Scholar 

  19. Gray, J.: Designing a Simple FPGA-Optimized RISC CPU and System-on-a-Chip. Gray Research LLC (2000), http://www.fpgacpu.org

  20. Buttazzo, G.C.: Rate monotonic vs. EDF: Judgement day. Real-Time Systems 29, 5–26 (2005)

    Article  MATH  Google Scholar 

  21. Rau, B.R., Fisher, J.A.: Instruction-level parallel processing: History, overview, and perspective. The Journal of Supercomputing 7(1 - 2), 9–50 (1993)

    Article  Google Scholar 

  22. Johnson, M.: Superscalar Microprocessor Design. Prentice-Hall, Englewood Cliffs (1991)

    Google Scholar 

  23. Torng, H.C., Vassiliadis, S. (eds.): Instruction Level Parallel Processors. IEEE Computer Society Press, Los Alamitos (1995)

    Google Scholar 

  24. Aditya, S., Mahlke, S.A., Rau, B.R.: Code Size Minimization and Retargetable Assembly for Custom EPIC and VLIW Instruction Formats, HPL-2000-141. HP Laboratories, Palo Alto (2000)

    Google Scholar 

  25. Aditya, S., Rau, B.R.: Automatic Architecture Synthesis and Compiler Retargeting for VLIW and EPIC Processors, HPL-1999-93. HP Laboratories, Palo Alto (1999)

    Google Scholar 

  26. Pillai, S., Jacome, M.F.: Compiler-directed ILP extraction for clustered VLIW/EPIC machines: Predication, speculation and modulo scheduling. In: Proceedings of the European Conference on Design, Automation and Test (DATE), Munich, Germany, pp. 422–427. IEEE Computer Society, Los Alamitos (2003)

    Google Scholar 

  27. Rajagopalan, S., Rajan, S.P., Malik, S., Rigo, S., Araujo, G., Takayama, K.: A retargetable VLIW compiler framework for DSPs with instruction-level parallelism. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20, 1319 (2001)

    Article  Google Scholar 

  28. Halambi, A., Grun, P., Ganesh, V., Khare, A., Dutt, N., Nicolau, A.: EXPRESSION: A language for architecture exploration through compiler/simulator retargetability. In: Proceedings of the European Conference on Design, Automation and Test (DATE), Munich, Germany, p. 485. IEEE Computer Society, Los Alamitos (1999)

    Google Scholar 

  29. Henzinger, T.A., Benjamin, H., Kirsch, C.M.: Embedded control systems development with giotto. SIGPLAN Notices 36, 64 (2001)

    Article  Google Scholar 

  30. Jie, L., Lee, E.A.: Timed multitasking for real-time embedded software. IEEE Control Systems Magazine 23, 65 (2003)

    Article  Google Scholar 

  31. Mellor, S.J.: Automatic code generation from UML models. C++ Report 11(4), 28–33 (1999); automatic code generation; UML; high-level language compilers; notation; object-oriented systems

    Google Scholar 

  32. Mwelwa, C., Pont, M.J., Ward, D.: Code generation supported by a pattern-based design methodology. In: Koelmans, A., Bystrov, A., Pont, M. (eds.) Proceedings of the 1st UK Embedded Forum, University of Newcastle upon Tyne, pp. 36–55 (2004)

    Google Scholar 

  33. Vidler, P.J., Pont, M.J.: Automatic conversion from ‘single processor’ to ‘multi-processor’ software architectures for embedded control systems. In: Koelmans, A., Bystrov, A., Pont, M.J., Ong, R., Brown, A. (eds.) Proceedings of the 2nd UK Embedded Forum (2005)

    Google Scholar 

  34. Ayavoo, D., Pont, M.J., Parker, S.: A ‘hardware-in-the-loop’ testbed representing the operation of a cruise-control system in a passenger car. In: Proceedings of the 2nd UK Embedded Forum (2005)

    Google Scholar 

  35. ISO/DIS 11898: Road Vehicles — Interchange of Digital Information — Controller Area Network (CAN) for High Speed Communication (1992)

    Google Scholar 

  36. Nahas, M., Short, M.J., Pont, M.J.: The impact of bit stuffing on the real-time performance of a distributed control system. In: Proceedings of the 10th International CAN Conference, Rome (2005)

    Google Scholar 

  37. Marti, P., Fuertes, J.M., Fohler, G.: A control performance metric for real-time timing constraints. In: Proceedings of the 14th Euromicro International Conference on Real-Time Systems (2002)

    Google Scholar 

  38. Dorf, R.C., Bishop, R.H.: Modern Control Systems, 7th edn. Addison-Wesley, Reading (1995)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Embedded Systems Laboratory, University of Leicester, University Road, LEICESTER, LE1 7RH, UK

    Peter J. Vidler & Michael J. Pont

Authors
  1. Peter J. Vidler
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Michael J. Pont
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Department of Computer Science, University of Calgary,, 2500 University Drive N.W., T2N 1N4, Calgary, AB, Canada

    Marina L. Gavrilova

  2. Department of Mathematics and Computer Science, University of Perugia, via Vanvitelli, 1, I-06123, Perugia, Italy

    Osvaldo Gervasi

  3. William Norris Professor, Head of the Computer Science and Engineering Department, University of Minnesota, USA

    Vipin Kumar

  4. OptimaNumerics Ltd.,, Cathedral House 23-31 Waring Street, BT1 2DX, Belfast, UK

    C. J. Kenneth Tan

  5. Clayton School of IT, Monash University, 3800, Clayton, Australia

    David Taniar

  6. Department of Chemistry, University of Perugia, Via Elce di Sotto, 8, I-06123, Perugia, Italy

    Antonio Laganá

  7. School of Computing, Soongsil University, Seoul, Korea

    Youngsong Mun

  8. School of Information and Communication Engineering, Sungkyunkwan University, Korea

    Hyunseung Choo

Rights and permissions

Reprints and permissions

Copyright information

© 2006 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Vidler, P.J., Pont, M.J. (2006). Computer Assisted Source-Code Parallelisation. In: Gavrilova, M.L., et al. Computational Science and Its Applications - ICCSA 2006. ICCSA 2006. Lecture Notes in Computer Science, vol 3984. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11751649_3

Download citation

  • DOI: https://doi.org/10.1007/11751649_3

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-34079-9

  • Online ISBN: 978-3-540-34080-5

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation