Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture

  • Ignacio Algredo-Badillo
  • Claudia Feregrino-Uribe
  • René Cumplido
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3982)


This work reports a non-pipelined AES (Advanced Encrypted Standard) FPGA (Field Programmable Gate Array) architecture, with low resource requirements. The architecture is designed to work on CBC (Cipher Block Chaining) mode and achieves a throughput of 1.45 Gbps. This implementation is a module of a configuration library for a Cryptographic Reconfigurable Platform (CRP).


Clock Cycle Field Programmable Gate Array Advance Encryption Standard Initial Round FPGA Resource 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Ignacio Algredo-Badillo
    • 1
  • Claudia Feregrino-Uribe
    • 1
  • René Cumplido
    • 1
  1. 1.National Institute for Astrophysics, Optics and ElectronicsSta. Ma. Tonantzintla, PueblaMéxico

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