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Application of LFSRs for Parallel Sequence Generation in Cryptologic Algorithms

  • Sourav Mukhopadhyay
  • Palash Sarkar
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3982)

Abstract

We consider the problem of efficiently generating sequences in hardware for use in certain cryptographic algorithms. The conventional method of doing this is to use a counter. We show that sequences generated by linear feedback shift registers (LFSRs) can be tailored to suit the appropriate algorithms. For hardware implementation, this reduces both time and chip area. As a result, we are able to suggest improvements to the design of DES Cracker built by the Electronic Frontier Foundation in 1998; provide an efficient strategy for generating start points in time-memory trade/off attacks; and present an improved parallel hardware implementation of a variant of the counter mode of operation of a block cipher.

Keywords

DES Cracker TMTO Counter Mode of Operation LFSR 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Sourav Mukhopadhyay
    • 1
  • Palash Sarkar
    • 1
  1. 1.Cryptology Research Group, Applied Statistics UnitIndian Statistical InstituteKolkataIndia

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