Abstract
Much of the chip area and power in a modern processor are used by mechanisms that compensate for slow main memory such as caches, out-of-order execution and prefetching. We attack this problem by utilizing a DRAM macro made by Hwang et. al that is faster than conventional DRAM macros, but does not conserve data in the DRAM cells after reading. Their prototype included a large write-back buffer for conserving data without degrading performance of read accesses. We eliminate this buffer by utilizing the already existing cache in processor designs at the cost of potential memory bank congestion. Two implementable and one theoretic upper-bound scheme for cache write-back are evaluated. We find that the size of the cache can be highly reduced without degrading performance when utilizing destructive-read DRAM. The large write-back buffer can be omitted when destructive-read DRAM is used with a processor with cache without significant degradation of performance.
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Draper, J., Kang, C.W., Kim, I., Daglikoca, G., Chame, J., Hall, M., Steele, C., Barrett, T., LaCoss, J., Granacki, J., Shin, J., Chen, C.: The architecture of the DIVA processing-in-memory chip. In: Proc. 16th ACM Int’l. Conf. Supercomp. (2002)
Elliott, D.G., Snelgrove, W.M., Stumm, M.: Computational RAM: A memory-SIMD hybrid and its application to DSP. In: CICC, Boston, MA (1992)
Gokhale, M., Holmes, B., Iobst, K.: Processing in memory; the Terasys massively parallel PIM array. IEEE Computer, 23–31 (1995)
Kirsch, G.: Active memory: Micron’s Yukon. In: Proceedings of the International, Parallel and Distributed Processing Symposium, p. 11 (2003)
Kang, Y., Huang, W., Yoo, S.M., Keen, D., Ge, Z., Lam, V., Patnaik, P., Torellas, J.: FlexRAM: Towards an advanced intelligent memory system. In: ICCD (1999)
Mai, K., Paaske, T., Jayasena, N., Ho, R., Dally, W., Horowitz, M.: Smart Memories: A modular reconfigurable architecture. In: ISCA (2000)
Nunomura, Y., Shimizu, T., Tomisawa, O.: M32R/D-integrating DRAM and microprocessor. Micro, IEEE 17(6), 40–48 (1997)
Oskin, M., Chong, F., Sherwood, T.: Active Pages: A model of computation for intelligent memory. In: Int. Symp. on Computer Arch., Barcelona, Spain (1998)
Saulsbury, A., Pong, F., Nowatzyk, A.: Missing the memory wall: the case for processor/memory integration. In: ISCA 1996. Proc. of the 23rd annual int. symp. on Computer architecture, pp. 90–101. ACM Press, New York (1996)
Yerosheva, L., Kuntz, S., Brockman, J., Kogge, P.: A microserver view of HTMT. In: Proc. 15th Int. Parallel and Distributed Processing Symposium (2001)
Gwennap, L.: Embedded DRAM use rises. Nikkei Electronics Asia (June 2003)
Furuyama, T.: Trends and challenges of large scale embedded memories. In: Custom Integrated Circuits Conference. Proceedings of the IEEE 2004, 449–456 (2004)
Hwang, C.L., Kirihata, T., Wordernan, M., et al.: A 2.9ns random access cycle embedded DRAM with a destructive-read architecture. In: IEEE Symp. on VLSI Circ., Digest of Tech. Pap., pp. 174–175 (2002)
Ji, B., Munetoh, S., Hwang, C.L., Wordeman, M., Kirihata, T.: Destructive-read random access memory system buffered with destructive-read memory cache for SoC applications. In: Symp. on VLSI Circuits, Dig. of Tech. Papers (2003)
Dybdahl, H., Kjeldsberg, P., Granns, M., Natvig, L.: Destructive-read in embedded DRAM, impact on power consumption. Journal of Embedded Computing, Special Issue on Embedded Single-Chip Multicore Architectures (2) (2006)
Austin, T., Larson, E., Ernst, D.: SimpleScalar: an infrastructure for computer system modeling. IEEE Computer 35(2) (2002)
KleinOsowski, A., Lilja, D.J.: MinneSPEC: A new SPEC benchmark workload for simulation-based computer architecture research. Comp. Archi. Letters 1 (2002)
Patterson, D., Anderson, T., Yelick, K.: A case for intelligent DRAM: IRAM. In: Hot Chips VIII, Palo Alto, CA, pp. 18–20 (1996)
Kogge, P., Sunaga, T., Miyataka, H., Kitamura, K., Retter, E.: Combined DRAM and logic chip for massively parallel systems. IEEE, Adv. Research in VLSI (1995)
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Dybdahl, H., Grannæs, M., Natvig, L. (2006). Cache Write-Back Schemes for Embedded Destructive-Read DRAM. In: Grass, W., Sick, B., Waldschmidt, K. (eds) Architecture of Computing Systems - ARCS 2006. ARCS 2006. Lecture Notes in Computer Science, vol 3894. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11682127_11
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DOI: https://doi.org/10.1007/11682127_11
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