Skip to main content
SpringerLink
Log in

Verification of Parameterized Timed Systems

  • Conference paper
Formal Modeling and Analysis of Timed Systems (FORMATS 2005)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 3829))

  • 492 Accesses

Abstract

One of the prominent methods for program verification is that of model checking [CES86,QS82]. In the last decade there has been an extensive research effort in order to extend the applicability of model checking to systems with infinite state spaces. There are at least two reasons why a system may be infinite-state:

– A system may operate on data structures with unbounded domains. Examples include real-valued clocks in timed automata [AD94], stacks in push-down automata [BEM97], queues in communicating processes [AJ96], counters in counter machines, etc.

– A system can also be infinite-state because it is parameterized. This means that the description of the system is parameterized by the number of components inside the system. In such a case, we would like to verify correctness of the system regardless of the number of processes.

We consider systems which contain both sources of infiniteness; namely parameterized systems of processes each of which behaves as a timed automaton.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Alur, R., Dill, D.: A theory of timed automata. Theoretical Computer Science 126, 183–235 (1994)

    Article  MATH  MathSciNet  Google Scholar 

  2. Abdulla, P.A., Deneux, J., Mahata, P.: Multi-clock timed networks. In: Proc. LICS 2004 IEEE Int. Symp. on Logic in Computer Science, pp. 345–354 (2004)

    Google Scholar 

  3. Abdulla, P.A., Deneux, J., Mahata, P.: Open, closed and robust timed networks. In: Proc. INFINITY 2004, 6th International Workshop on Verification of Infinite-State Systems (2004)

    Google Scholar 

  4. Abdulla, P.A., Jonsson, B.: Verifying programs with unreliable channels. Information and Computation 127(2), 91–101 (1996)

    Article  MATH  MathSciNet  Google Scholar 

  5. Abdulla, P.A., Jonsson, B.: Model checking of systems with many identical timed processes. Theoretical Computer Science 290(1), 241–264 (2003)

    Article  MATH  MathSciNet  Google Scholar 

  6. Abdulla, P.A., Jonsson, B., Nilsson, M., Saksena, M.: A survey of regular model checking. In: Gardner, P., Yoshida, N. (eds.) CONCUR 2004. LNCS, vol. 3170, pp. 348–360. Springer, Heidelberg (2004)

    Chapter  Google Scholar 

  7. Abdulla, P.A., Legay, A., d’Orso, J., Rezine, A.: Simulation-based iteration of tree transducers. In: Halbwachs, N., Zuck, L.D. (eds.) TACAS 2005. LNCS, vol. 3440, pp. 30–44. Springer, Heidelberg (2005)

    Chapter  Google Scholar 

  8. Bouajjani, A., Esparza, J., Maler, O.: Reachability Analysis of Pushdown Automata: Application to Model Checking. In: Mazurkiewicz, A., Winkowski, J. (eds.) CONCUR 1997. LNCS, vol. 1243. Springer, Heidelberg (1997)

    Google Scholar 

  9. Bengtsson, J., Griffioen, W.O.D., Kristoffersen, K.J., Larsen, K.G., Larsson, F., Pettersson, P., Yi, W.: Verification of an audio protocol with bus collision using UPPAAL. In: Alur, R., Henzinger, T.A. (eds.) CAV 1996. LNCS, vol. 1102, pp. 244–256. Springer, Heidelberg (1996)

    Google Scholar 

  10. Boigelot, B., Legay, A., Wolper, P.: Iterating transducers in the large. In: Hunt Jr., W.A., Somenzi, F. (eds.) CAV 2003. LNCS, vol. 2725, pp. 223–235. Springer, Heidelberg (2003)

    Chapter  Google Scholar 

  11. Bouajjani, A., Touili, T.: Extrapolating Tree Transformations. In: Brinksma, E., Larsen, K.G. (eds.) CAV 2002. LNCS, vol. 2404, p. 539. Springer, Heidelberg (2002)

    Chapter  Google Scholar 

  12. Clarke, E.M., Emerson, E.A., Sistla, A.P.: Automatic verification of finite-state concurrent systems using temporal logic specification. ACM Trans. on Programming Languages and Systems 8(2), 244–263 (1986)

    Article  MATH  Google Scholar 

  13. German, S.M., Sistla, A.P.: Reasoning about systems with many processes. Journal of the ACM 39(3), 675–735 (1992)

    Article  MATH  MathSciNet  Google Scholar 

  14. Kesten, Y., Maler, O., Marcus, M., Pnueli, A., Shahar, E.: Symbolic model checking with rich assertional languages. Theoretical Computer Science 256, 93–112 (2001)

    Article  MATH  MathSciNet  Google Scholar 

  15. Lynch, N.A., Shavit, N.: Timing-based mutual exclusion. In: IEEE Real-Time Systems Symposium, pp. 2–11 (1992)

    Google Scholar 

  16. Mason, I.A., Talcott, C.L.: Simple network protocol simulation within maude. In: Futatsugi, K. (ed.) Electronic Notes in Theoretical Computer Science, vol. 36. Elsevier, Amsterdam (2001)

    Google Scholar 

  17. Queille, J.P., Sifakis, J.: Specification and verification of concurrent systems in cesar. In: Dezani-Ciancaglini, M., Montanari, U. (eds.) Programming 1982. LNCS, vol. 137, pp. 337–352. Springer, Heidelberg (1982)

    Google Scholar 

  18. Schneider, F.B., Bloom, B., Marzullo, K.: Putting time into proof outlines. In: Huizing, C., de Bakker, J.W., Rozenberg, G., de Roever, W.-P. (eds.) REX 1991. LNCS, vol. 600. Springer, Heidelberg (1992)

    Chapter  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Uppsala University, Sweden

    Parosh Aziz Abdulla

Authors
  1. Parosh Aziz Abdulla
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Department of Information Technology, Uppsala University, P.O. Box 337, SE-751 05, Uppsala, Sweden

    Paul Pettersson

  2. Department of Information Technology, Uppsala University, Sweden

    Wang Yi

Rights and permissions

Reprints and permissions

Copyright information

© 2005 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Abdulla, P.A. (2005). Verification of Parameterized Timed Systems. In: Pettersson, P., Yi, W. (eds) Formal Modeling and Analysis of Timed Systems. FORMATS 2005. Lecture Notes in Computer Science, vol 3829. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11603009_8

Download citation

  • DOI: https://doi.org/10.1007/11603009_8

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-30946-8

  • Online ISBN: 978-3-540-31616-9

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation