Abstract
With the goal to make the wireless sensor network nodes small in size, light in weight, cheap in cost, as well as low in power consumption, projects have been carried out to study the hardware and software co-design and to develop sensor node SOC technology. We have proposed a general “sensor node on a chip” approach, namely EasiSOC, with two typical SOC architectures for different application areas. The first architecture of sensor node supports basic functionalities which performs relatively simple tasks with fixed routines. The second architecture of sensor node favors complex functionalities and advanced jobs. Current research progresses on the development of the first SOC structures are also introduced.
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Huang, X., Zhao, Z., Cui, L. (2005). EasiSOC: Towards Cheaper and Smaller. In: Jia, X., Wu, J., He, Y. (eds) Mobile Ad-hoc and Sensor Networks. MSN 2005. Lecture Notes in Computer Science, vol 3794. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11599463_23
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DOI: https://doi.org/10.1007/11599463_23
Publisher Name: Springer, Berlin, Heidelberg
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