Abstract
The demand of integration of many heterogeneous semiconductor intellectual property (IP) blocks has been introducing a new chip design paradigm so called on chip network. This paradigm promisingly offers a packet switched network among IPs to reduce the main problems in the very deep sub micron technologies that arise from non-scalable global wire delay, failure to achieve global synchronization, errors due to the signal integrity, non-scalable bus based functional interconnection, etc. This paper introduces interconnected or switched network topologies and also analyze their performances in terms of communication protocol related to the issues such as routing strategy, buffer size, routing algorithm , etc. The above mentioned evaluations are done by utilizing the tool that has been widely used in the research domain of computer network design, so called NS-2.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Benini, L., DeMicheli, G.: Networks On Chips: A new SoC paradigm. IEEE Computer (January 2002)
Horowitz, M.A., et al.: The future of wires. Proceeding of IEEE 89(4), 490–504 (2001)
Guerrier, P., Grenier, A.: A generic architecture for on-chip packet-switched interconnectio. In: Design automation and test in Europe conference, August 2000, pp. 250–256 (2000)
Petrini, F., Vanneschi, M.: Network performance under Physical Constrain. In: Proceedings of International Conference on Parallel Processing, August 1997, pp. 34–43 (1997)
Leiserson, C.E.: Fat Trees: Universal networks for hardware efficient supercomputing. IEEE Transactions on Computer, C-34, 892–890 (1985)
Kariniemi, H., Nurmi, J.: New adaptive routing algorithm for extended generalized fat trees on-chip. In: Proceedings of International Symposium on System-on-Chip, November 2003, pp. 113–118 (2003)
Pande, P.P., Grecu, C., Ivanov, A., Saleh, R.: Design of a switch for network on chip applications. In: Proceedings of the 2003 International Symposium on Circuits and Systems, May 2003, vol. 5, pp. V-217–V-220 (2003)
Sun, Y.-R., Kumar, S., Jantsch, A.: Simulation and Evaluation for a Network on Chip Architecture Using Ns-2. In: Proceeding of 20th IEEE Norchip Conference (November 2002)
Berozzi, D., Benini, L., DeMicheli, G.: Low-Power Error Resilient Encoding for On-chip Data Buses. In: DATE-International Conference on Design and Test Europe (June 2002)
Muttersbach, J., et al.: Globally-asynchronous locally synchronous architectures to simplify the design of on-chip systems. In: Proc. 12th Annual IEEE International ASIC/SoC Conference, September 1999, pp. 317–321 (1999)
Bertsekas, D., Gallager, R.: Data Networks, 2nd edn., ch. 5. Prentice-Hall, Inc., Englewood Cliffs (1992)
Murali, S., De Micheli, G.: Bandwidth-Constrained Mapping of Cores pnto NoC Architectures. In: DATE, International Conference on Design and Test Europe, pp. 896–901 (2004)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Ngo, VD., Nguyen, HN., Choi, HW. (2005). Analyzing the Performance of Mesh and Fat-Tree Topologies for Network on Chip Design. In: Yang, L.T., Amamiya, M., Liu, Z., Guo, M., Rammig, F.J. (eds) Embedded and Ubiquitous Computing – EUC 2005. EUC 2005. Lecture Notes in Computer Science, vol 3824. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11596356_32
Download citation
DOI: https://doi.org/10.1007/11596356_32
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-30807-2
Online ISBN: 978-3-540-32295-5
eBook Packages: Computer ScienceComputer Science (R0)