Abstract
In this paper, a high performance asynchronous on-chip bus designed in a Globally Asynchronous Locally Synchronous (GALS) style is proposed. The asynchronous on-chip bus is capable of handling multiple outstanding transactions and in-order completion to achieve a high performance, which is implemented with distributed and modularized control unit in a layered interface. The architecture of asynchronous on-chip bus is discussed and implemented for simulations. Simulation results show that throughput of the proposed asynchronous on-chip bus with multiple outstanding transactions and in-order transaction completion is increased by 31.3%, while power consumption overhead is only 6.76%, as compared to an asynchronous on-chip bus with a single outstanding transaction.
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Jung, EG., Hong, EP., Jhang, KS., Lee, JA., Har, DS. (2005). Self-timed Interconnect with Layered Interface Based on Distributed and Modularized Control for Multimedia SoCs. In: Ho, YS., Kim, H.J. (eds) Advances in Multimedia Information Processing - PCM 2005. PCM 2005. Lecture Notes in Computer Science, vol 3767. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11581772_44
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DOI: https://doi.org/10.1007/11581772_44
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-30027-4
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