Advertisement

Energy Efficient United L2 Cache Design with Instruction/Data Filter Scheme

  • Zhiqiang Ma
  • Zhenzhou Ji
  • Mingzeng Hu
  • Yi Ji
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3756)

Abstract

The on-chip caches usually consume a significant amount of energy in modern microprocessors. This paper presents an I/D filter scheme to reduce the energy consumption of united L2 caches shared by instructions and data. By adding an I/D indicator bit, the cache block is classified into I-block and D-block. For instruction and data accesses, only the corresponding blocks instead of all the blocks in the same set selected are accessed. By this method, we can easily filter the unnecessary way activities and save the energy consumption. This technique uses a small amount of additional hardware without increasing the cache access latency, and the area overhead is negligible. Simplescalar simulator and CACTI were used to evaluate the performance of our proposed architecture, the results shows that the I/D filter scheme is energy efficient for set-associative caches.

Keywords

World Line Area Overhead Cache Block Cache Access Filter Scheme 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Edmondson, J.F., et al.: Internal Organization of the Alpha 21164, A 300-MHz 64-bit Quad-issue CMOS RISC Microprocessor. Digital Tech. J. 7 (1995)Google Scholar
  2. 2.
    Montenaro, J., et al.: A 160MHz 32b 0.5W CMOS RISC Microprocessor. In: Int. Solid-State Circuits Conf. (1996)Google Scholar
  3. 3.
    Su, C.L., Despain, A.M.: Cache Design for Energy Efficiency. In: Proc. 28th Int. System Sciences Conf. (1995)Google Scholar
  4. 4.
    Ghose, K., Kamble, M.B.: Reducing Power in Superscalar Processor Caches Using Subbanking, Multiple Line Buffers and Bit-line Segmentation. In: Proc. Int. Low Power Electronics and Design Symp. (1999)Google Scholar
  5. 5.
    Kin, J., Gupta, M., Mangione-Smith, W.H.: The Filter Cache: An Energy Efficient Memory Structure. In: Proc. 30th Int. Microarchitecture Symp., pp. 184–193 (1997)Google Scholar
  6. 6.
    Ranganathan, P., Adve, S., Jouppi, N.: Reconfigurable CACHEs and their Application to Media Processing. In: International Symposium on Computer Architecture (IACA), pp. 214–224 (2000)Google Scholar
  7. 7.
    Albonesi, D.H.: Selective CACHE Ways: On Demand CACHE Resource Allocation. In: IEEE/ACM International Symposium on Microarchitecture (MICRO-32), pp. 248–259 (1999)Google Scholar
  8. 8.
    Yang, J., Gupta, R.: Energy Efficient Frequent Value Data Cache Design. In: Int. Symp. on Microarchitecture (2002)Google Scholar
  9. 9.
    Zhang, C., Yang, J., Vahid, F.: Low Static-Power Frequent-Value Data Caches. In: Design, Automation and Test in Europe Conference (DATE 2004), Paris, France, pp. 214–219 (2004)Google Scholar
  10. 10.
    Villa, L., Zhang, M., Asanovic, K.: Dynamic Zero Compression for Cache Energy Reduction. In: IEEE/ACM International Symposium on Microarchitecture (MICRO-33), pp. 214–220 (2000)Google Scholar
  11. 11.
    Inoue, K., Ishihara, T., Murakami, K.: Way-predicting Set-associative Cache for High Performance and Low Energy Consumption. In: Proc. Int. Low Power Electronics and Design Symp., pp. 273–275 (1999)Google Scholar
  12. 12.
    Chang, Y.J., Lai, F., Ruan, S.J.: An Efficient Two-level Filter Scheme for Low Power Cache. In: IEEE/ACM 11th Int. Logic and Synthesis Workshop, New Orleans, LA (2002)Google Scholar
  13. 13.
    Burge, D., Austin, T.: The Simplescalar Tool Set, Version 2.0. Technical Report CS-TR-97-1342, Univ. of Wisconsin, Madison (1997)Google Scholar
  14. 14.
    Shivakumar, P., Jouppi, N.: CACTI 3.0: An Integrated Cache Timing, Power, and Area Model. COMPAQ Western Research Lab (2001)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Zhiqiang Ma
    • 1
  • Zhenzhou Ji
    • 1
  • Mingzeng Hu
    • 1
  • Yi Ji
    • 1
  1. 1.Department of Computer Science and Technology of Harbin Institute of TechnologyHarbinChina

Personalised recommendations