Abstract
Adaptable silicon area usage within an integrated pixel processing array is a key issue for embedded single instruction, multiple data (SIMD) image processing architectures due to limited chip resources and varying application requirements. In this regard, this paper explores the effects of varying the number of vector (multichannel) pixels mapped to each processing element (VPPE) within a SIMD architecture. The VPPE ratio has a significant impact on the overall area and energy efficiency of the computational array. Moreover, this paper evaluates the impact of our color-aware instruction set (CAX) on each VPPE configuration to identify ideal grain size for a given SIMD system extended with CAX. CAX supports parallel operations on two-packed 16-bit (6:5:5) YCbCr (luminance-chrominance) data in a 32-bit datapath processor, providing greater concurrency and efficiency for vector processing of color image sequences. Experimental results for 3-D vector quantization indicate that high processing performance with the lowest cost is achieved at VPPE = 16 with CAX.
This work was performed by authors at the Georgia Institute of Technology (Atlanta, GA).
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References
Bellaouar, A., Elmasry, M.I.: Low-Power Digital VLSI Design: Circuits and Systems. Kluwer Academic, Boston (1995)
Bond, S., Jung, S., Vendier, O., Brooke, M., Jokerst, N.M., Chai, S., Lopez-Lagunas, A., Wills, D.S.: 3D stacked Si CMOS VLSI smart pixels using through-Si optoelectronic interconnections. In: Proc. IEEE Lasers and Electro-Optics Soc. Summer Topical Meeting on Smart Pixels, pp. 27–28 (1998)
Chai, S.M., Taha, T.M., Wills, D.S., Meindl, J.D.: Heterogeneous architecture models for interconnect-motivated system desig. IEEE Trans. VLSI Systems, special issue on system level interconnect prediction 8(6), 660–670 (2000)
Coding of Moving Pictures and Audio. ISO/IEC JTC1/SC29/WG11 N3312 (2000)
Fossum, E.R.: Digital camera system on a chip. IEEE Micro 18(3), 8–15 (1998)
Fossum, E.R.: Architectures for Focal Plane Image Processing. Optical Engineering 28(8), 865–871 (1989)
Gentile, A., Sander, S., Wills, L.M., Wills, D.S.: Impact of pixel to processing ratio in embedded SIMD image processing architectures. Journal of Parallel and Distributed Computing 64(11), 1318–1332 (2004)
Gersho, A., Gray, R.M.: Vector Quantization and Signal Compression. Kluwer Academic, Dordrecht (1992)
Gonzalez, R.C., Woods, R.E.: Digital Image Processing. Prentice Hall, Englewood Cliffs (2002)
Hang, H.-M., Haskell, B.G.: Interpolative vector quantization of color images. IEEE Transactions on Communications 36(4), 465–470 (1988)
Herbordt, M.C., Anand, A., Kidwai, O., Sam, R., Weems, C.C.: Processor/ memory/ array size tradeoffs in the design of SIMD arrays for a spatially mapped workload. In: Proc. IEEE Intl. Workshop on Computer Architecture for Machine Perception, pp. 12–21 (1997)
The international technology roadmap for semiconductors (2003), http://public.itrs.net
Kim, J.: Architectural enhancements for color image and video processing on embedded systems. PhD dissertation, Georgia Inst. of Technology (2005)
Kim, J., Wills, D.S.: Evaluating a 16-bit YCbCr (6:5:5) color representation for low memory, embedded video processing. In: Proc. of the IEEE Conf. on Consumer Electronics, pp. 181–182 (2005)
Kwatra, S.C., Lin, C.M., Whyte, W.A.: An adaptive algorithm for motion compensated color image coding. IEEE Trans. Commun. COM-35, 747–754 (1987)
Lee, R.B.: Subword parallelism with MAX-2. IEEE Micro 16(4), 51–59 (1996)
MIPS extension for digital media with 3D, Technical Report, MIPS technologies, Inc. (1997), http://www.mips.com
MMXTM Technology Technical Overview, http://www.x86.org/intel.doc/mmxmanuals.htm
Nugent, S., Wills, D.S., Meindl, J.D.: A hierarchical block-based modeling methodology for SoC in GENESYS. In: Proc. of the 15th Ann. IEEE Intl. ASIC/SOC Conf., pp. 239–243 (2002)
Peleg, A., Weiser, U.: MMX technology extension to the Intel architecture. IEEE Micro 16(4), 42–50 (1996)
Plataniotis, K.N., Venetsanopoulos, A.N.: Color Image Processing and Applications. Springer, Heidelberg (2000)
Suh, J., Prasanna, V.K.: An efficient algorithm for out-of-core matrix transposition. IEEE Trans. on Computers 51(4), 420–438 (2002)
Tremblay, M., O’Connor, J.M., Narayanan, V., He, L.: VIS speeds new media processing. IEEE Micro, 10–20 (1996)
Yang, C.C.: Effects of coordinate systems on color image processing. MS Thesis, University of Arizona, Tucson (1992)
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Kim, J., Wills, D.S., Wills, L.M. (2005). Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing Architectures. In: Srikanthan, T., Xue, J., Chang, CH. (eds) Advances in Computer Systems Architecture. ACSAC 2005. Lecture Notes in Computer Science, vol 3740. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11572961_45
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DOI: https://doi.org/10.1007/11572961_45
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