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High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design

  • Petr Matoušek
  • Aleš Smrčka
  • Tomáš Vojnar
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3725)

Abstract

The paper presents high-level modelling and formal analysis and verification on an FPGA-based multigigabit network monitoring system called Scampi. Uppaal was applied in this work to establish some correctness and throughput results on a model intentionally built using patterns reusable in other similar projects. Some initial experiments with parametric analysis using TReX were performed too.

Keywords

Time Slot Read Time Incoming Request FIFO Queue Executive Component 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

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    Bouajjani, A., Collomb-Annichini, A., Sighireanu, M.: TReX: A tool for Reachability Analysis of Complex Systems. In: Berry, G., Comon, H., Finkel, A. (eds.) CAV 2001. LNCS, vol. 2102, p. 368. Springer, Heidelberg (2001)CrossRefGoogle Scholar
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    Holeček, J., Kratochvíla, T., Rehák, V., Šafránek, D., Simeček, P.: How to Formalize FPGA Hardware Design. Technical Report 4/2004, CESNET (October 2004)Google Scholar
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    Matoušek, P., Smrčka, A., Vojnar, T.: High-Level Modeling, Analysis, and Verification of Scampi2. Technical report, CESNET (2005) (to appear)Google Scholar
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    Novotný, J., Fučík, O., Antoš, D.: Project of IPv6 Router with FPGA Hardware Accelerator. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778. Springer, Heidelberg (2003)CrossRefGoogle Scholar
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    Pettersson, P., Larsen, K.G.: Uppaal2k. In: Bulletin of the European Association for Theoretical Computer ScienceGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Petr Matoušek
    • 1
  • Aleš Smrčka
    • 1
  • Tomáš Vojnar
    • 1
  1. 1.FITBrno University of TechnologyBrnoCzech Republic

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