High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design

  • Petr Matoušek
  • Aleš Smrčka
  • Tomáš Vojnar
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3725)


The paper presents high-level modelling and formal analysis and verification on an FPGA-based multigigabit network monitoring system called Scampi. Uppaal was applied in this work to establish some correctness and throughput results on a model intentionally built using patterns reusable in other similar projects. Some initial experiments with parametric analysis using TReX were performed too.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Petr Matoušek
    • 1
  • Aleš Smrčka
    • 1
  • Tomáš Vojnar
    • 1
  1. 1.FITBrno University of TechnologyBrnoCzech Republic

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