Abstract
In this paper we present an innovative clustering technique which is combined with a simple tool configuration search aimed at power minimisation in LUT (look-up table)-based FPGAs. The goal of our technique is to reduce the capacitance on high power consuming nets by including as many of these nets as possible inside clusters wherein they can be routed on low capacitance lines. We introduce two new metrics for identifying power critical nets based on the switching activity and the number of net-segments that can be totally absorbed by a cluster. The results of our method show an average reduction of 32.8% with a maximum reduction of 48.9% in the net power over that achieved by Xilinx’s ISE 5.3i tools.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Wolff, F.G., Knieser, M.J., Weyer, D.J., Papachristou, C.A.: High-Level Low Power FPGA Design Methodology. In: NAECON 2000: IEEE National Aerospace and Electronics Conference, Dayton, OH, October 2000, pp. 554–559 (2000)
Chen, C.-S., Hwang, T.-T., Liu, C.L.: Low Power FPGA Design - A Re-engineering Approach. In: DAC-34: ACM/IEEE Design Automation Conference, Anaheim, CA, June 1997, pp. 656–661 (1997)
Hwang, J.-M., Chiang, F.-Y., Hwang, T.-T.: A Re-engineering Approach to Low Power FPGA Design Using SPFD. In: DAC-35: ACM/IEEE Design Automation Conference, San Francisco, CA, June 1998, pp. 722–725 (1998)
Kumthekar, B., Benini, L., Macii, E., Somenzi, F.: Power Optimisation of FPGA-based designs without rewiring. IEE Proceedings on Computers and Digital Techniques 147(3), 167–174 (2000)
Doyle, C., Launders, S.: A Circuit Clustering Technique Aimed at Reducing the Total Amount of Interconnect Resource used in an FPGA. In: Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Stará Lesná, Slovakia, April 18-21, pp. 211–214 (2004)
Shang, L., Kaviani, A.S., Bathala, K.: Dynamic Power Consumption in Virtex-II FPGA Family. In: FPGA 2002: ACM/SIGDA 10th Int. Symposium on FPGAs, Monterey, CA, February 2002, pp. 157–164 (2002)
Kusse, E., Rabaey, J.: Low-Energy Embedded FPGA Structures. In: ISLPED 1998: IEEE International Symposium on Low Power Electronics and Design, Monterey, CA, August 1998, pp. 155–160 (1998)
Singh, A., Marek-Sadowska, M.: Efficient Circuit Clustering for Area and Power Reduction in FPGAs. In: FPGA 2002: ACM/SIGDA 10th Int. Symposium on FPGAs, Monterey, CA, February 2002, pp. 59–66 (2002)
Alexander, M.J.: Power Optimization for FPGA Look-Up Tables. In: ISPD 1997: ACM/IEEE International Symposium on Physical Design, Napa Valley, CA, April 1997, pp. 156–162 (1997)
A Set of RT- and Gate-level Benchmarks by The CAD Group at Politecnico di Torino: download http://www.cad.polito.it/tools/#bench
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Launders, S., Doyle, C., Cooper, W. (2005). Switching-Activity Directed Clustering Algorithm for Low Net-Power Implementation of FPGAs. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_43
Download citation
DOI: https://doi.org/10.1007/11556930_43
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29013-1
Online ISBN: 978-3-540-32080-7
eBook Packages: Computer ScienceComputer Science (R0)