Abstract
In this paper, we propose a hardware/software partitioning method for improving performance in single-chip embedded systems comprised by processor and Field Programmable Gate Array reconfigurable logic. Speedups are achieved by executing critical software parts on the reconfigurable logic. A generic hybrid System-on-Chip platform, which can model existing processor-FPGA systems, is considered. The partitioning flow utilizes an automated analysis procedure at the basic-block level for detecting kernels in software. Three different instances of the considered generic platform and two sets of benchmarks are used in the experiments. For the systems composed by 32-bit processors the speedup of five applications ranges from 1.3 to 3.7 relative to an all software solution. For an 8-bit platform, the speedups of eight DSP algorithms are considerably greater, since they range from 3.2 to 68.4.
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References
Callahan, T.J., et al.: The Garp Architecture and C Compiler. IEEE Computer 33(4), 62–69 (2000)
Hauck, S., et al.: The Chimaera Reconfigurable Functional Unit. IEEE Trans. on VLSI Syst. 12(2), 206–217 (2004)
Virtex FPGAs, Xilinx Inc. (2005), http://www.xilinx.com
Excalibur, Altera Inc. (2005), http://www.altera.com
FPSLIC, ATMEL Inc. (2005), http://www.atmel.com
Gajski, D.D., et al.: SpecSyn: An environment supporting the specify-explore-refine paradigm for hardware/software system design. IEEE Trans. on VLSI Syst. 6(1), 84–100 (1998)
Henkel, J.: A low power hardware/software partitioning approach for core-based embedded systems. In: Proc. of the 36th ACM/IEEE DAC, pp. 122–127 (1999)
Ye, A., et al.: A C Compiler for a Processor with a Reconfigurable Functional Unit. In: Proc. of FPGA, pp. 95–100 (2000)
Bazargan, K., et al.: A C to Hardware/Software Compiler. In: Proc. of FCCM, pp. 331–332 (2000)
Villareal, J., et al.: Improving Software Performance with Configurable Logic. Design Automation for Embedded Systems 7, 325–339 (2002)
Stitt, G., Vahid, F.: Energy Advantages of Microprocessors Platforms with On-Chip Configurable Logic. IEEE Design & Test of Computers 19(6), 36–43 (2002)
Honeywell Inc. (2005), http://www.htc.honeywell.com/projects/acsbench
Synplify Pro, Synplicity Inc. (2005), http://www.synplicity.com
SUIF2 compiler infrastucture (2005), http://suif.stanford.edu/suif/suif2/index.html
MachineSUIF (2005), http://www.eecs.harvard.edu/hube/research/machsuif.html
SimpleScalar LLC (2005), http://www.simplescalar.com
IAR Embedded Workbench, IAR Systems Inc. (2005), http://www.iar.com
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Galanis, M.D., Dimitroulakos, G., Goutis, C.E. (2005). Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCs. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_26
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DOI: https://doi.org/10.1007/11556930_26
Publisher Name: Springer, Berlin, Heidelberg
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