Abstract
The load-store queue (LQ-SQ) of modern superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed and memory access becomes worse, the capacity requirements for the LQ-SQ increase, and its design becomes a challenge due to its CAM structure. In this paper we propose an efficient load-store queue state filtering mechanism that provides a significant energy reduction (on average 35% in the LSQ and 3.5% in the whole processor), and only incurs a negligible performance loss of less than 0.6%.
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Castro, F., Chaver, D., Pinuel, L., Prieto, M., Huang, M.C., Tirado, F. (2005). A Power-Efficient and Scalable Load-Store Queue Design. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_1
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DOI: https://doi.org/10.1007/11556930_1
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29013-1
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